NCP5359ADR2G;NCP5359AMNR2G;NCP5359AMNTBG;中文规格书,Datasheet资料

Gate Driver for NotebookPower Systems

The NCP5359A is a high performance dual MOSFET gate driveroptimized to drive the gates of both high−side and low−side powerMOSFETs in a synchronous buck converter. Each of the drivers candrive up to 3 nF load with a 25 ns propagation delay and 15 nstransition time.

Adaptive nonoverlap and power saving operation circuit canprovide a low switching loss and high efficiency solution for notebookand desktop systems.

A high floating top driver design can accommodate VBST voltageas high as 35 V, with transient voltages as high as 35 V. BidirectionalEN pin can provide a fault signal to controller when the gate driverfault detect under OVP, UVLO occur. Also, an undervoltage lockoutfunction guarantees the outputs are low when supply voltage is low,and a thermal shutdown function provides the IC withovertemperature protection.

Features

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MARKINGDIAGRAMS

88

1ALYWG

SOIC−8D SUFFIXCASE 751

5359AALYW G1= Assembly Location= Wafer Lot= Year

= Work Week

= Pb−Free PackageDFN8MN SUFFIXCASE 506AA

••••••••••

Faster Rise and Fall TimesThermal Shutdown ProtectionAdaptive Nonoverlap Circuit

Floating Top Driver Accommodates Boost Voltages of up to 30 VOutput Disable Control Turns Off Both MOSFETsComplies with VRM 11.1 SpecificationsUndervoltage Lockout

Power Saving Operation Under Light Load ConditionsThermally Enhanced PackageThese are Pb−Free Devices

11

AA= Device CodeM= Date Code

G= Pb−Free Package

PIN CONNECTIONS

BSTPWMENVCC

1BSTPWMENVCC

(Top View)

8DRVHSWGNDDRVL

1

8

DRVHSWGNDDRVL

Typical Applications

•Power Solutions for Desktop and Notebook Systems

ORDERING INFORMATION

DeviceNCP5359ADR2GNCP5359AMNR2GNCP5359AMNTBG

PackageSOIC−8(Pb−Free)DFN8(Pb−Free)DFN8(Pb−Free)

Shipping†2500 Tape & Reel3000 Tape & Reel3000 Tape & Reel

© Semiconductor Components Industries, LLC, 2009

†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationBrochure, BRD8011/D.

1

Publication Order Number:

NCP5359A/D

September, 2009 − Rev. 1

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AA MG4

NCP5359A

BST

VCCChipENLevel ShiftandDriverDRVHENFaultPWMDRVH ComparatorPWM > 2.2 V = 1, Else = 0Falling Edge Delay1.0 VUVLOThermal ShutdownFPWM Comparator0.8 V < PWM < 2.2 V = 1, Else 0ENPre −Over voltagePre−OV2 V/1 VFalling Edge DelayRQSQDriverPre−OV+−FaultChipENSW1 mVl++−ChipENGNDVCCDRVLFigure 1. Internal Block Diagram

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+−+lSWl+GNDNCP5359A

4 V to 15 VBSTPWMEN

10 V to 13.2 V

PWMENVCCDRVHSWGNDDRVLVOUTFigure 2. Typical Application

PIN DESCRIPTION

SOIC−812

DFN812

SymbolBSTPWM

Description

Upper MOSFET Floating Bootstrap Supply Pin

PWM Input Pin

When PWM voltage is higher than 2.2 V, DRVH will set to 1 and DRVL set to 0When PWM voltage is lower than 0.8 V, DRVL will set to 1 and DRVH set to 0When 0.8 V < PWM < 2.2 V and SW < 0, DRVL will set to 1When 0.8 V < PWM < 2.2 V and SW > 0, DRVL will set to 0

Enable Pin

When OVP, TSD or UVLO has happened, the gate driver will pull the pin to lowConnect to Input Power Supply 10 V to 13.2 VLow Side Gate Drive OutputGround PinSwitch Node Pin

High Side Gate Drive Output

345678

345678

ENVCCDRVLGNDSWDRVH

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NCP5359A

MAXIMUM RATINGS

Rating

Thermal Characteristics, Plastic PackageThermal Resistance Junction−to−AirOperating Junction Temperature RangeOperating Ambient Temperature RangeStorage Temperature RangeMoisture Sensitivity Level

SOIC−8DFN8

SOIC−8

(20.2 sq mm, 2 oz Cu) DFN8

SymbolRqJA

Value1783300 to +1500 to +85− 55 to +150

11

Unit°C/W

TJTATstgMSL

°C°C°C−

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.

MAXIMUM RATINGS

Pin Symbol

VccBST

Pin Name

Main Supply Voltage InputBootstrap Supply voltage

VMAX15 V

35 V wrt / GND40 V ≤ 50 ns wrt / GND

15 V wrt / SW35 V wrt / GND40 V ≤ 50 ns wrt / GNDBST + 0.3 V

35 V ≤ 50 ns wrt / GND

15 V wrt / SW

Vcc + 0.3 V

6 V6 V0 V

VMIN−0.3 V−0.3 V wrt / SW

SWDRVH

Switching Node

(Bootstrap Supply Return)High Side Driver Output

−1 VDC−10 V (200 ns)−0.3 V wrt / SW−2 V (200 ns) wrt / SW

−0.3 V−5 V (200 ns)

−0.3 V−0.3 V0 V

DRVLPWMENGND

Low Side Driver OutputDRVH and DRVL Control Input

Enable PinGround

1.Latchup Current Maximum Rating: 100 mA per JEDEC standard: JESD78.2.Moisture Sensitivity Level (MSL): 1&3 per IPC/JEDEC standard: J−STD−020A.3.The maximum package power dissipation limit must not be exceeded.

PD+

NOTE:

TJ(max)*TA

RqJAThis device is ESD sensitive. Use standard ESD precautions when handling.

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NCP5359A

ELECTRICAL CHARACTERISTICS (VCC = 10 V − 13.2 V, TA = 0°C to +85°C, VEN = 5 V unless otherwise noted)

Characteristics

Supply VoltageVCC Operating VoltagePower ON Reset thresholdSupply Current

VCC Quiescent Supply Current in NormalOperation

VCC Standby Current

BST Quiescent Supply Current in NormalOperation

BST Standby CurrentUndervoltage LockoutVCC Start ThresholdVCC UVLO HysteresisOutput Overvoltage Trip Threshold atStartupEN Input

Input Voltage HighInput Voltage LowHysteresis (Note 4)Enable Pin Sink CurrentPropagation Delay Time (Note 4)PWM Input

DRVH Comparator Drop ThresholdPWM Input Self Bias VoltageDRVL Comparator Rise ThresholdInput CurrentHigh Side Driver

Output Resistance, SourcingOutput Resistance, SinkingOutput Resistance, unbiased (Note 4)SW Pull Down Resistance (Note 4)Transition Time (Note 6)Propagation Delay (Notes 4 & 5)Low Side Driver

Output Resistance, SourcingOutput Resistance, Sinking

Output Resistance, unbiased (Note 4)Transition Time (Note 6)Propagation Delay (Notes 4 & 5)Negative Current Detector ThresholdThermal ShutdownThermal ShutdownThermal Shutdown HysteresisTsdTsdhys

(Note 6)(Note 6)15017020°C°CtrDRVLtfDRVLtpdhDRVLtpdlDRVLVNCDTRH_BGRL_BG

SW = GNDSW = VCCBST − SW = 0 VCLOAD = 3 nFCLOAD = 3 nFDriving High, CLOAD = 3 nFDriving Low, CLOAD = 3 nF(Note 6)

1015−1.0

1016152.01.0

3.52.55525203535mVnsWWkWnstrDRVHtfDRVHtpdhDRVHtpdlDRVHRH_TGRL_TG

VBST – VSW = 12 VVBST – VSW = 12 VBST − SW = 0 VSW to GNDCLOAD = 3 nF, VBST – VSW = 12 VCLOAD = 3 nF, VBST – VSW = 12 VDriving High, CLOAD = 3 nFDriving Low, CLOAD = 3 nF1015101016152.01.03.52.5555525203530nsWWkWkWnsVTH_DRVHVPWMVTH_DRVLIPWM

PWM = 0 V, EN = GND302.21.41.51.60.8VVVmAVEN_HIVEN_LOWVEN_HYSIEN_SINKtpdhENtpdlEN

VCC = 5.5 V4.020206060500

2.0

1.0VVmVmAnsnsVCCTHVCCHYSOVPSUPower Startup time, VCC > 9 V.(Without trimming)

1.88.28.71.02.09.5VVVIVCC_NORMIVCC_SBCIBST1_normalIBST2_normalIBST1_SDIBST2_SD

EN = 5 V, PWM = OSC, FSW = 100 kCLOAD = 0 p

EN = GND; No switchingPWM = +5 V, SW = 0 VPWM = GND, SW = 0 VPWM = +5 VPWM = GND5.00.51.01.00.250.258.02.51.81.8mAmAmAmAVCCVPOR

102.813.2VVSymbol

Test Conditions

Min

Typ

Max

Units

4.Guaranteed by design; not tested in production .

5.For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low.6.Design guaranteed.

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NCP5359A

Table 1. DECODER TRUTH TABLE

PWM Input

Greater than 2.2 V

Greater than 0.8 V, but less than 2.2 VGreater than 0.8 V, but less than 2.2 VLess than 0.8 V

ZCDX

High (current through MOSFET is greater than 0)Low (current through MOSFET is less than 0)

X

DRVLLowHighLowHigh

DRVHHighLowLowLow

PWM

DRVLtpdlDRVL90%2 VtfDRVL90%10%tpdhDRVHtrDRVH90%tpdlDRVH90%2 V10%tpdhDRVLtfDRVH10%trDRVLDRVH−SW10%SW

Figure 3.

PWM

DRVH−SW

DRVL

IL

Figure 4. Timing Diagram

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NCP5359A

APPLICATION INFORMATION

The NCP5359A gate driver is a single phase MOSFETdriver designed for driving two N−channel MOSFETs in asynchronous buck converter topology. This driver iscompatible with the NCP3418B gate drive. This gate drivesoperation is similar with the NCP3418B, but has twoadditional new features: Bidirection fault detection andmultilevel PWM input. When the gate driver works withON Semiconductor’s NCP5392 controller, it can provide adifference output logic status through multi−level PWMinput. For this new feature, higher efficiency can beprovided. For the bidirection fault detection function, it isused to provide a driver state information to other gatedrivers and controller in a multiphase buck converter. e.govervoltage protection (OVP) function at startup, thermalshutdown and undervoltage lockout (UVLO). This featurecan provide an additional protection function for themulti−phase system when the fault condition occurs in onechannel. With this additional feature, converter overallsystem will be more reliable and safe.

Enable Pin

Power ON reset

Power on reset feature is used to protect a gate driver avoidabnormal status driving the startup condition. When theinitial soft−start voltage is higher than 3.2 V, the gate driverwill monitor the switching node SW pin. If SW pin high than1.9 V, bottom gate will be force to high for discharge theoutput capacitor. The fault mode will be latch and EN pinwill force to be low, unless the driver is recycle. When inputvoltage is higher than 9 V, the gate driver will normaloperation, top gate driver DRVH and bottom gate driver willfollow the PWM signal decode to a status.

Adaptive Nonoverlap

The bidirection enable pin is connected with an open drainMOSFET. This pin is controlled by internal or externalsignal. There are three conditions will be triggered:

1.The voltage at SWN pin is higher than presetvoltage at power startup.

2.The controller hits the UVLO at VCC pin.3.The controller hits the thermal shutdown.

When the internal fault has been detected, EN pin will bepull low. In this case, the drive output DRVH and DRVL willbe forced low, until the fault mode remove then restartautomatic.

Undervoltage Lockout

The nonoverlap dead time control is used to avoid theshoot through damage the power MOSFETs. When thePWM signal pull high, DRVL will go low after apropagation delay, the controller will monitors the switchingnode (SWN) pin voltage and the gate voltage of theMOSFET to know the status of the MOSFET. When the lowside MOSFET status is off an internal timer will delay turnon of the high–side MOSFET. When the PWM pull low, gateDRVH will go low after the propagation delay (tpd DRVH).The time to turn off the high side MOSFET is depending onthe total gate charge of the high−side MOSFET. A timer willbe triggered once the high side MOSFET is turn off to delaythe turn on the low−side MOSFET.

Layout Guidelines

The DRVH and DRVL are held low until VCC reaches 9 Vduring startup. The PWM signals will control the gate statuswhen VCC threshold is exceeded. If VCC decreases to 3.2 Vbelow the threshold, the output gate will be forced low untilinput voltage VCC rises above the startup threshold.

Layout is very important thing for design a DC−DCconverter. Bootstrap capacitor and VCC capacitor are mostcritical items, it should be placed as close as to the driver IC.Another item is using a GND plane. Ground plane canprovide a good return path for gate drives for reducing theground noise. Therefore GND pin should be directlyconnected to the ground plane and close to the low−sideMOSFET source pin. Also, the gate drive trace should beconsidered. The gate drives has a high di/dt when switching,therefore a minimized gate drives trace can reduce the di/dv,raise and fall time for reduce the switching loss.

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NCP5359A

PACKAGE DIMENSIONS

SOIC−8CASE 751−07ISSUE AJ

−X−NOTES:

1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.

2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A AND B DO NOT INCLUDEMOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6.751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

MILLIMETERSMINMAX4.805.003.804.001.351.750.330.511.27 BSC0.100.250.190.250.401.270 _8 _0.250.505.806.20INCHES

MINMAX0.10.1970.1500.1570.0530.0690.0130.0200.050 BSC0.0040.0100.0070.0100.0160.0500 _8 _0.0100.0200.2280.244A85B1S40.25 (0.010)

MY

M−Y−GKC−Z−HD0.25 (0.010)

MSEATINGPLANENX 45_0.10 (0.004)MJZY

SX

SDIMABCDGHJKMNSSOLDERING FOOTPRINT*

1.520.0607.00.27.00.1550.60.0241.2700.050SCALE 6:1

mmǓǒinches*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

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NCP5359A

PACKAGE DIMENSIONS

DFN8MN SUFFIXCASE 506AA−01

ISSUE D

DABPIN ONEREFERENCENOTES:

1.DIMENSIONING AND TOLERANCING PERASME Y14.5M, 1994 .

2.CONTROLLING DIMENSION: MILLIMETERS.3.DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN0.25 AND 0.30 MM FROM TERMINAL.

4.COPLANARITY APPLIES TO THE EXPOSEDPAD AS WELL AS THE TERMINALS.

DIMAA1A3bDD2EE2eKLMILLIMETERSMINMAX0.801.000.000.050.20 REF0.200.302.00 BSC1.101.302.00 BSC0.700.900.50 BSC0.20−−−0.250.35E2 X0.10C2 X0.10CTOP VIEW0.10C8 X

A(A3)Ce18 X40.08CSEATINGPLANEA1SIDE VIEWD2e/2LE2K858 Xb0.10CAB0.05CNOTE 3BOTTOM VIEW

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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