2001
µPD72873Firewarden™ ROADMAP
Firewarden SeriesOHCI LinkµPD72862IEEE1394-1995Core DevelopmentOHCI LinkµPD72861OHCI LinkµPD72860LinkCore1-ChipOHCI+PHYµPD728721-ChipOHCI+PHYµPD72870A,72870B1-ChipOHCI 1.1+PHYµPD728741-ChipOHCI 1.1+PHYµPD728731-ChipOHCI+PHYµPD728702
Preliminary Data Sheet S15305EJ1V0DS
µPD72873BLOCK DIAGRAMS
01pnpnpnpnss00001111aaiiAABBAABBBBpppppppppp01TTTTTTTTTTRRXIXOrrrtleeetoaotmiol0l1gnttP_AVbtbtDDrradearsaLktlaaCootnrlreyliLedmcatrPCPoaunrcPsnsoelVCeGCsyanaOSrCnTeGealaontdtniaranPC0othDariDrtncc e r etidPC1aroaieemCMgovitidtimocPC2b eLeoesrdnnAntccaRaeeaEtrSRDTKP_RESETCOP_DVLDDBe cersleYkanfbutrHiawCPSLeCoatPSP tnIGNDGNDKCeOYcLHafrBPe tn IKNILeeMcaGROM_ENneGROM_SCLiOfrOrrhRe/IoccettnGROM_SDACaisIi gkMogn eLeiLtaRtSOOOdreFFFRnOllIIIFFFSaFAor TTRCmIMt oFIAIC Dno CtPCI_VDDrnneeeroirllrIcICaoemetllaetL_VDDfweoIrsiPrOCrt/IPnogtCrug etonPanPginofeICaMCnoRCKTTLNQTE3LL1EPNCSSEENEYEYPE3RRRNPRR_PMNRGMMUOABDSDOATDARRUPS_SIRCRRSTIVTDSNIAPEERI CDRPFo EoPSK3ttL D DR00CAEDCBACPreliminary Data Sheet S15305EJ1V0DS
3
µPD72873Application Information
Power delivery for D3cold wake up support (D3CSUP = ‘High’)
(a) System suspend
ATX Power Unit
5 VDual Switch5V SB3.3 V RegulatorDual Switch3.3 VPCI_VDD(PC is 3.3 V PCI system.)Resume ResetCircuitRSMRSTPCI_VDD (System is 5 V PCI system.)System 5 VD3CSUPL_VDDRSMRSTPCI_VDDIEEE1394 BusPIN_ENPCI_VDDPCI BusChip SetRSMRSTµPD72873
(b) System resume
ATX Power Unit
5 VDual Switch5V SB3.3 V RegulatorDual Switch3.3 VPCI_VDD(System is 3.3 V PCI system.)Resume ResetCircuitRSMRSTPCI_VDD (System is 5 V PCI system.)System 5 VD3CSUPL_VDDRSMRSTPCI_VDDIEEE1394 BusPIN_ENPCI_VDDPCI BusChip SetRSMRSTµPD72873
4
Preliminary Data Sheet S15305EJ1V0DS
µPD72873PIN CONFIGURATION (TOP VIEW)
• 120-pin plastic TQFP (Fine pitch) (14 x 14)
µPD72873GC-9EV
GNDCARD_ONGROM_ENGROM_SCLGROM_SDAIC(L)D3CSUPGNDP_AVDDP_AVDDP_AVDDGNDGNDGNDGNDTpA1pTpA1nTpB1pTpB1nTpA0pTpA0nTpB0pTpB0nTpBias1TpBias0P_AVDDGNDCPSRI1RI0L_VDDCLKRUNPMEINTAPRSTPCLKGNTREQAD31AD30GNDAD29AD28L_VDDAD27AD26AD25AD24PCI_VDDGNDCBE3IDSELAD23AD22L_VDDAD21AD20AD19AD18GND1201191181171161151141131121111101091081071061051041031021011009997969594939291123456710111213141516171819202122232425262728293090888786858483828180797877767574737271706968676665636261P_AVDDGNDXOXIP_AVDDIC(N)GNDGNDP_DVDDP_RESETIC(L)P_DVDDIC(L)IC(L)IC(L)PIN_ENRSMRSTP_DVDDPC2PC1PC0GNDAD0AD1AD2AD3L_VDDAD4AD5GNDL_VDDAD17AD16CBE2FRAMEIRDYTRDYGNDDEVSELSTOPPERRSERRL_VDDPARCBE1GNDAD15AD14AD13AD12L_VDDAD11AD10GNDAD9AD8CBE0AD7AD6PCI_VDD313233343536373839404142434447484950515253555657585960Preliminary Data Sheet S15305EJ1V0DS
5
µPD72873PIN NAME
AD0 to AD31: PCI Multiplexed Address and DataCARD_ON: PCI/Card SelectCBE0 toCBE3CLKRUNCPSD3CSUPDEVSELFRAMEGNDGNT: PCICLK Running: Cable Power Status Input: D3cold Support: Device Select: Cycle Frame: GND
: Bus_master Grant: Command/Byte Enables
PMEPRSTP_AVDDP_DVDDP_RESETPIN_ENREQRI0RI1RSMRSTSERRSTOPTpA0nTpA0pTpA1nTpA1pTpB0nTpB0pTpB1nTpB1pTpBias0TpBias1TRDYXIXO
: PME Output: Reset
: PHY Analog VDD: PHY Digital VDD
: PHY Power on Reset Input: Pin Enable Input: Bus_master Request
: Resistor0 for Reference Current Setting: Resistor1 for Reference Current Setting: Resume Reset: System Error: PCI Stop
: Port-1 Twisted Pair A Negative Input/Output: Port-1 Twisted Pair A Positive Input/Output: Port-2 Twisted Pair A Negative Input/Output: Port-2 Twisted Pair A Positive Input/Output: Port-1 Twisted Pair B Negative Input/Output: Port-1 Twisted Pair B Positive Input/Output: Port-2 Twisted Pair B Negative Input/Output: Port-2 Twisted Pair B Positive Input/Output: Port-1 Twisted Pair Bias Voltage Output: Port-2 Twisted Pair Bias Voltage Output: Target Ready: X’tal XI: X’tal XO
GROM_EN: Serial EEPROM EnableGROM_SCL: Serial EEPROM Clock OutputGROM_SDA: Serial EEPROM Data Input / OutputIC(L)IC(N)IDSELINTAIRDYL_VDDPARPC0 to PC2PCI_VDDPCLKPERR: Internally Connected (Low Clamped): Internally Connected (Open): ID Select: Interrupt: Initiator Ready
: VDD for Link Digital Core and Link I/Os: Parity
: Power Class Input: VDD for PCI I/Os: PCI Clock: Parity Error
6
Preliminary Data Sheet S15305EJ1V0DS
µPD72873CONTENTS
1. PIN FUNCTIONS.....................................................................................................................................91.1 PCI/Cardbus Interface Signals: (52 pins)......................................................................................91.2 PHY Signals: (15 pins)..................................................................................................................111.3 PHY Control Signals: (4 pins).......................................................................................................111.4 PCI/Cardbus Select Signal: (1 pin)...............................................................................................111.5 Serial ROM Interface Signals: (3 pins).........................................................................................121.6 D3cold Wake Up Function Signals: (3 pins)...............................................................................121.7 IC: (6 pins)......................................................................................................................................121.8 VDD..................................................................................................................................................131.9 GND.................................................................................................................................................132. PHY REGISTERS...................................................................................................................................142.1 Complete Structure for PHY Registers........................................................................................142.2 Port Status Page (Page 000).........................................................................................................172.3 Vendor ID Page (Page 001)...........................................................................................................182.4 Vendor Dependent Page (Page 111 : Port_select 0001)............................................................183. CONFIGURATION REGISTERS..........................................................................................................193.1 PCI Bus Mode Configuration Register (CARD_ON = Low)........................................................19
3.1.1 Offset_00 Vendor ID Register...........................................................................................................203.1.2 Offset_02 Device ID Register............................................................................................................203.1.3 Offset_04 Command Register...........................................................................................................203.1.4 Offset_06 Status Register.................................................................................................................213.1.5 Offset_08 Revision ID Register.........................................................................................................223.1.6 Offset_09 Class Code Register.........................................................................................................223.1.7 Offset_0C Cache Line Size Register.................................................................................................223.1.8 Offset_0D Latency Timer Register....................................................................................................223.1.9 Offset_0E Header Type Register......................................................................................................223.1.10 Offset_0F BIST Register..................................................................................................................223.1.11 Offset_10 Base Address 0 Register................................................................................................233.1.12 Offset_2C Subsystem Vendor ID Register......................................................................................233.1.13 Offset_2E Subsystem ID Register...................................................................................................233.1.14 Offset_34 Cap_Ptr Register............................................................................................................233.1.15 Offset_3C Interrupt Line Register....................................................................................................233.1.16 Offset_3D Interrupt Pin Register.....................................................................................................243.1.17 Offset_3E Min_Gnt Register...........................................................................................................243.1.18 Offset_3F Max_Lat Register...........................................................................................................243.1.19 Offset_40 PCI_OHCI_Control Register...........................................................................................243.1.20 Offset_60 Cap_ID & Next_Item_Ptr Register..................................................................................243.1.21 Offset_62 Power Management Capabilities Register......................................................................253.1.22 Offset_ Power Management Control/Status Register..................................................................26
3.2 CardBus Mode Configuration Register (CARD_ON = High)......................................................27
3.2.1 Offset_14/18 Base Address 1/2 Register (Cardbus Status Registers)..............................................283.2.2 Offset_28 Cardbus CIS Pointer.........................................................................................................293.2.3 Offset_80 CIS Area...........................................................................................................................29
Preliminary Data Sheet S15305EJ1V0DS
7
µPD728734. PHY FUNCTION....................................................................................................................................304.1 Cable Interface...............................................................................................................................30
4.1.1 Connections.........................................................................................................................................304.1.2 Cable Interface Circuit..........................................................................................................................314.1.3 CPS......................................................................................................................................................314.1.4 Unused Ports........................................................................................................................................31
4.2 PLL and Crystal Oscillation Circuit.............................................................................................31
4.2.1 Crystal Oscillation Circuit.....................................................................................................................314.2.2 PLL.......................................................................................................................................................31
4.3 PC0 to PC2.....................................................................................................................................314.4 P_RESET........................................................................................................................................314.5 RI0, RI1...........................................................................................................................................315. ELECTRICAL SPECIFICATIONS.........................................................................................................326. PACKAGE DRAWING..........................................................................................................................357. RECOMMENDED SOLDERING CONDITIONS...................................................................................36
8
Preliminary Data Sheet S15305EJ1V0DS
µPD728731. PIN FUNCTIONS
1.1 PCI/Cardbus Interface Signals: (52 pins)
(1/2)NamePARI/OI/O44Pin No.IOLPCI/CardbusVolts(V)5/3.3FunctionParity is even parity across AD0 to AD31 and CBE0to CBE3. It is an input when AD0 to AD31 is aninput; it is an output when AD0 to AD31 is an output.Block *LinkAD0 to AD31I/O9, 10, 12, 13,15 to 18, 23, 24,26 to 29. 32. 33.47to 50, 52, 53,55, 56, 58, 59, 62,63, 65 to 68PCI/Cardbus5/3.3PCI Multiplexed Address and DataLinkCBE0 toCBE3FRAMEI/O21, 34, 45, 57-5/3.3Command/Byte Enables are multiplexed buscommands & byte enables.LinkI/O35PCI/Cardbus5/3.3Frame is asserted by the initiator to indicate thecycle beginning and is kept asserted during theburst cycle. If Cardbus mode (CARD_ON = 1), thispin should be pulled up to VDD.LinkTRDYI/O37PCI/Cardbus5/3.3Target Ready indicates that the current data phaseof the transaction is ready to be completed.LinkIRDYI/O36PCI/Cardbus5/3.3Initiator Ready indicates that the current busmaster is ready to complete the current data phase.During a write, its assertion indicates that theinitiator is driving valid data onto the data bus.During a read, its assertion indicates that theinitiator is ready to accept data from the currently-addressed target.LinkREQO8PCI/Cardbus5/3.3Bus_master Request indicates to the bus arbiterthat this device wants to become a bus master.LinkGNTI7-5/3.3Bus_master Grant indicates to this device thataccess to the bus has been granted.LinkIDSELI22-5/3.3Initialization Device Select is used as chip selectfor configuration read/write transaction during thephase of device initialization. If Cardbus mode(CARD_ON = 1), this pin should be pulled up to VDD.LinkDEVSELI/O39PCI/Cardbus5/3.3Device Select when actively driven, indicates thatthe driving device has decoded its address as thetarget of the current access.LinkSTOPI/O40PCI/Cardbus5/3.3PCI Stop when actively driven, indicates that thetarget is requesting the current bus master to stopthe transaction.LinkPMEO3PCI/Cardbus5/3.3PME Output for power management event.LinkRemark*:If the Link pin is pulled up, it should be connected to L_VDD.
Preliminary Data Sheet S15305EJ1V0DS
9
µPD72873(2/2)NameCLKRUNI/OI/O2Pin No.IOLPCI/CardbusVolts(V)5/3.3FunctionPCICLK Running as input, to determine the statusof PCLK; as output, to request starting or speedingup clock.Block *LinkINTAPERROI/O441PCI/CardbusPCI/Cardbus5/3.35/3.3Interrupt the PCI interrupt request A.Parity Error is used for reporting data parity errorsduring all PCI transactions, except a special cycle.It is an output when AD0 to AD31 and PAR are bothinputs. It is an input when AD0 to AD31 and PARare both outputs.LinkLinkSERRO42PCI/Cardbus5/3.3System Error is used for reporting address parityerrors, data parity errors during the special cycle, orany other system error where the effect can becatastrophic. When reporting address parity errors,it is an output.LinkPRSTPCLKII56--5/3.35/3.3Reset PCI resetPCI Clock 33 MHz system bus clock.LinkLinkRemark*:If the Link pin is pulled up, it should be connected to L_VDD.
10
Preliminary Data Sheet S15305EJ1V0DS
µPD728731.2 PHY Signals: (15 pins)
NameTpA0pTpA0nTpB0pTpB0nTpA1pTpA1nTpB1pTpB1nCPSTpBias0TpBias1RI0RI1XIXO
I/OI/OI/OI/OI/OI/OI/OI/OI/OIOO--IO
101100999810510410310293969791928788
Pin No.
IOL---------------Volts(V)---------------Function
Port-1 Twisted Pair A Positive Input/Output Note 1Port-1 Twisted Pair A Negative Input/Output Note 1Port-1 Twisted Pair B Positive Input/Output Note 1Port-1 Twisted Pair B Negative Input/Output Note 1Port-2 Twisted Pair A Positive Input/Output Note 1Port-2 Twisted Pair A Negative Input/Output Note 1Port-2 Twisted Pair B Positive Input/Output Note 1Port-2 Twisted Pair B Negative Input/Output Note 1Cable Power Status Input Note2
Port-1 Twisted Pair Bias Voltage Output Note 1Port-2 Twisted Pair Bias Voltage Output Note 1Resistor0 for Reference Current Setting Note 3Resistor1 for Reference Current Setting Note 3X’tal XIX’tal XO
Block *PHY AnalogPHY AnalogPHY AnalogPHY AnalogPHY AnalogPHY AnalogPHY AnalogPHY AnalogPHY DigitalPHY AnalogPHY AnalogPHY AnalogPHY AnalogPHY AnalogPHY Analog
Notes1.If unused port, please refer to 4.1.4 Unused Ports.
2.Please refer to 4.1.3 CPS.3.Please refer to 4.5 RI0, RI1.
Remark*:If the PHY Digital pin is pulled up, it should be connected to P_DVDD.
If the PHY Analog pin is pulled up, it should be connected to P_AVDD.
1.3 PHY Control Signals: (4 pins)
NamePC0 to PC2P_RESETI/OIIPin No.70 to 7281IOL--Volts(V)3.3-FunctionPower Class Input Note 1PHY Power on Reset Input Note 2Block *PHY DigitalPHY DigitalNotes1.Please refer to 4.3 PC0 to PC2.2.Please refer to 4.4 P_RESET.Remark*:If the PHY Digital pin is pulled up, it should be connected to P_DVDD.
1.4 PCI/Cardbus Select Signal: (1 pin)
NameCARD_ON
I/OI
119
Pin No.
IOL-Volts(V)3.3
PCI/CardBus Select1:Cardbus mode0:PCI bus mode
Function
Block *Link
Remark*:If the Link pin is pulled up, it should be connected to L_VDD.
Preliminary Data Sheet S15305EJ1V0DS
11
µPD728731.5 Serial ROM Interface Signals: (3 pins)
NameGROM_SDAGROM_SCLGROM_EN
I/OI/OOI
116117118
Pin No.
IOL6 mA6 mA-Volts(V)3.33.33.3
Function
Serial EEPROM Data Input / OutputSerial EEPROM Clock OutputSerial EEPROM Enable1: GUID Load enable0: GUID Load disable
Block *LinkLinkLink
Remark*:If the Link pin is pulled up, it should be connected to L_VDD.
1.6 D3cold Wake Up Function Signals: (3 pins)
NameD3CSUPI/OI114Pin No.IOL-Volts(V)5/3.3D3cold Support 1: D3cold wake up enable 0: D3cold wake up disableRSMRSTI74-5/3.3Resume ResetD3cold support (114 pin) = ‘1’As this mode supports D3cold wake up,RSMRST must connect system RSMRSTsignal. D3cold support (114 pin) = ‘0’As this mode is the µPD72872 compatible,RSMRST clamp to ‘1’.PIN_ENI75-5/3.3Pin Enable InputD3cold support (114 pin) = ‘1’As this mode supports D3cold wake up,PIN_EN must connect non backup powersources. For example no backup power VDD isPCI_VDD.D3cold support (114 pin) = ‘0’ As this mode is the µPD72872 compatible,PIN_EN clamp to ‘1’.LinkLinkFunctionBlock *LinkRemark*:If the Link pin is pulled up, it should be connected to L_VDD.
1.7 IC: (6 pins)
NameIC(L)IC(N)
I/OI-Pin No.76 to 78, 80, 11585
IOL--Volts(V)--Function
Internally Connected (Low clamped)Internally Connected (Open)
Block--
12
Preliminary Data Sheet S15305EJ1V0DS
µPD728731.8 VDD
NamePCI_VDDL_VDD
I/O--Pin No.19, 60
1, 14, 25, 31, 43,51,
IOL--Volts(V)5/3.33.3
VDD for PCI I/Os
VDD for Link digital Core and Link I/Os
To use D3cold wake up function, L_VDD must switchVDD to Vaux when the system suspend.
P_DVDDP_AVDD
--73, 79, 8286, 90, 95,110 to 112
--3.33.3
PHY digital VDDPHY Analog VDD
PHY DigitalPHY Analog
Function
Block *LinkLink
Remark*:If the Link pin is pulled up, it should be connected to L_VDD.
If the PHY Digital pin is pulled up, it should be connected to P_DVDD.If the PHY Analog pin is pulled up, it should be connected to P_AVDD.
1.9 GND
NameGND
I/O-Pin No.11, 20, 30, 38, 46,, 61, 69, 83, 84,, 94, 106 to 109,113, 120
IOL-Volts(V)-GND
Function
Block-
Preliminary Data Sheet S15305EJ1V0DS
13
µPD728732. PHY REGISTERS
2.1 Complete Structure for PHY Registers
Figure 2-1. Complete Structure of PHY Registers
0
0000000100100011010001010110011110001001101010111100110111101111
Page_select
Link_activeWatchdogRHB
IBRExtended (7)Max_speedContenderISBR
Loop
ReservedReservedJitterPwr_fail
Timeout
Port_event
1
2
Physical_ID
Gap_count
Total_portsDelay
Pwr_classEnab_accel
Enab_multi
3
4
5
6R
7PS
Reserved
Reserved
Register0 (page_select)Register1 (page_select)Register2 (page_select)Register3 (page_select)Register4 (page_select)Register5 (page_select)Register6 (page_select)Register7 (page_select)
Port_select
Table 2-1. Bit Field Description (1/3)
FieldPhysical_IDR
Size61
R/WRR
Reset value0000000
Description
Physical_ID value selected from Self_ID period.If this bit is 1, the node is root.1: Root0: Not root
PS
1
R
Cable power status.1: Cable power on0: Cable power off
RHBIBR
11
R/WR/W
00
Root Hold -off bit. If 1, becomes root at the bus reset.Initiate bus reset.
Setting to 1 begins a long bus reset.Long bus reset signal duration: 166 µsec.Returns to 0 at the beginning of bus reset.
Gap_count
6
R/W
111111
Gap count value.
It is updated by the changes of transmitting and receiving the PHYconfiguration packet Tx/Rx.
The value is maintained after first bus reset.After the second bus reset it returns to reset value.
Extended
3
R
111
Shows the extended register map.
14
Preliminary Data Sheet S15305EJ1V0DS
µPD72873Table 2-1. Bit Field Description (2/3)
FieldTotal_ports
Size4
R/WR
Reset value
0011
Supported port number.0010: 2 ports
Max_speed
3
R
010
Indicate the maximum speed that this node supports.010: 98.304, 196.608 and 393.216 Mbps
DelayLink_active
41
RR/W
00001
Indicate worst case repeating delay time. 144 + (Delay x 20) = 144 nsecLink active.1: Enable0: Disable
The logical AND status of this bit and LPS.State will be referred to “L bit” of Self-ID Packet#0.
The LPS is a PHY/Link interface signal and is defined in P1394a-2000. It isan internal signal in the µPD72873.
Contender
1
R/W
0
Contender.
“1” indicate this node support bus manager function. This bit will be referredto “C bit” of Self-ID Packet#0.
JitterPwr_class
33
RR/W
010SeeDescription
The difference of repeating time (Max.-Min.). (2+1) x 20=60 nsecPower class.
Please refer to IEEE1394a-2000 [4.3.4.1].
This bit will be referred to Pwr field of Self-ID Packet#0.
Watchdog
1
R/W
0
Watchdog Enable.
This bit serves two purposes.
When set to 1, if any one port does resume, the Port_event bit becomes 1.To determine whether or not an interrupt condition shall be indicated to thelink. On condition of LPS = 0 and Watchdog = 0, LKON as interrupt of Loop,Pwr_fail, Timeout is not output.
ISBR
1
R/W
0
Initiate short (arbitrated) bus reset.
Setting to 1 acquires the bus and begins short bus reset.Short bus reset signal output : 1.3 µsecReturns to 0 at the beginning of the bus reset.
Loop
1
R/W
0
Loop detection output.1: Detection
Writing 1 to this bit clears it to 0.Writing 0 has no effect.
Pwr_fail
1
R/W
1
Power cable disconnect detect.
It becomes 1 when there is a change from 1 to 0 in the CPS bit.Writing 1 to this bit clears it to 0.Writing 0 has no effect.
Description
Preliminary Data Sheet S15305EJ1V0DS
15
µPD72873Table 2-1. Bit Field Description (3/3)
FieldTimeout
Size1
R/WR/W
Reset value
0
Description
Arbitration state machine time-out.Writing 1 to this bit clears it to 0.Writing 0 has no effect.
Port_event
1
R/W
0
Set to 1 when the Int_enable bit in the register map of each port is 1 andthere is a change in the ports connected, Bias, Disabled and Fault bits.Set to 1 when the Watchdog bit is 1 and any one port does resume.Writing 1 to this bit clears it to 0.Writing 0 has no effect.
Enab_accel
1
R/W
0
Enables arbitration acceleration.
Ack-acceleration and Fly-by arbitration are enabled.1: Enabled0: Disabled
If this bit changes while the bus request is pending, the operation is notguaranteed.
Enab_multi
1
R/W
0
Enable multi-speed packet concatenation.
Setting this bit to 1 follows multi-speed transmission.
When this bit is set to 0,the packet will be transmitted with the same speedas the first packet.
Page_select
3
R/W
000
Select page address between 1000 to 1111.000: Port Status Page001: Vendor ID Page111: Vendor Dependent PageOthers: Unused
Port_select
4
R/W
0000
Port Selection.
Selecting 000 (Port Status Page) with the Page_select selects the port.Selecting 111 (Vendor Dependent Page) with the Page_select have to selectthe Port 1.0000: Port 00001: Port 1Others: Unused
Reserved
-R
000…
Reserved. Read as 0.
16
Preliminary Data Sheet S15305EJ1V0DS
µPD728732.2 Port Status Page (Page 000)
Figure 2-2. Port Status Page
0
10001001101010111100110111101111
AStat
Negotiated_speed
1
2
BStat
Int_enable
3
4ChildFault
5Connected
6BiasReserved
7Disabled
ReservedReservedReservedReservedReservedReserved
Table 2-2. Bit Field Description
FieldAStat
Size2
R/WR
Reset value
XX
A port status value.00: invalid, 10: “0”01: “1”, 11: “Z”
BStat
2
R
XX
B port status value.00: invalid, 10: “0”01: “1”, 11: “Z”
Child
1
R
Child node status value.1: Connected to child node0: Connected to parent node
Connected
1
R
0
Connection status value.1: Connected0: Disconnected
Bias
1
R
Bias voltage status value.1: Bias voltage0: No bias voltage
Disabled
1
R/W
SeeDescription
Negotiated_Speed
3
R
Shows the maximum data transfer rate of the node connected to this port.000: 100 Mbps001: 200 Mbps010: 400 Mbps
Int_enable
1
R/W
0
When set to 1, the Port_event is set to 1 if any of this port's Connected, Bias,Disabled or Fault bits change state.
Fault
1
R/W
0
Set to 1 if an error occurs during Suspend/Resume.Writing 1 to this bit clears it to 0.Writing 0 has no effect.
Reserved
-R
000…
Reserved. Read as 0.
The reset value is set to 0: Enabled.
Description
Preliminary Data Sheet S15305EJ1V0DS
17
µPD728732.3 Vendor ID Page (Page 001)
Figure 2-3. Vendor ID Page
0
10001001101010111100110111101111
Product_IDVendor_ID
1
2
3
4
5
6
7
Compliance_level
Reserved
Table 2-3. Bit Field Description
FieldCompliance_levelVendor_IDProduct_IDReserved
Size82424-R/WRRRR
000…Reset value0000000100004CH
According to IEEE1394a-2000.
Company ID Code value, NEC IEEE OUI.Product code.Reserved. Read as 0.
Description
2.4 Vendor Dependent Page (Page 111 : Port_select 0001)
Figure 2-4. Vendor Dependent Page
0
10001001101010111100110111101111
Reg_array
1
2
3
4
5
6
7
Table 2-4. Bit Field Description
FieldReg_array
Size
R/WR/W
Reset value
0
Description
This register array is possible R/W.
18
Preliminary Data Sheet S15305EJ1V0DS
µPD728733. CONFIGURATION REGISTERS
3.1 PCI Bus Mode Configuration Register (CARD_ON = Low)
31
24
23
16
15
08
07
00
Device IDVendor ID00HStatus
Command
04H
Class Code
Revision ID
08HBIST
Header Type
Latency Timer
Cache Line Size
0CHBase Address 010HReserved14HReserved18HReserved1CHReserved20HReserved24HReserved
28HSubsystem ID
Subsystem Vendor ID
2CHReserved
30HReserved
Cap_Ptr
34HReserved
38HMax_Lat
Min_Gnt
Interrupt Pin
Interrupt Line3CHPCI_OHCI_Control
40HReserved44HReserved48HReserved4CHReserved50HReservedHReserved58HReserved
5CHPower Management Capabilities
Next_Item_Ptr
Cap_ID60HReserved
Power Management Control/Status
HReserved
68HFCH
Preliminary Data Sheet S15305EJ1V0DS
19
µPD728733.1.1 Offset_00 Vendor ID Register
This register identifies the manufacturer of the µPD72873. The ID is assigned by the PCI_SIG committee.
Bits15-0
R/WR
Constant value of 1033H.
Description
3.1.2 Offset_02 Device ID Register
This register identifies the type of the device for the µPD72873. The ID is assigned by NEC Corporation.
Bits15-0
R/WR
Constant value of 00E7H.
Description
3.1.3 Offset_04 Command Register
The register provides control over the device’s ability to generate and respond to PCI cycles.
Bits01R/WRR/WDescriptionI/O enable Constant value of 0. The µPD72873 does not respond to PCI I/O accesses.Memory enable Default value of 1. It defines if the µPD72873 responds to PCI memoryaccesses. This bit should be set to one upon power-up reset.0: The µPD72873 does not respond to PCI memory cycles1: The µPD72873 responds to PCI memory cycles2R/WMaster enable Default value of 1. It enables the µPD72873 as bus-master on the PCI-bus.0: The µPD72873 cannot generate PCI accesses by being a bus-master1: The µPD72873 is capable of acting as a bus-master3RSpecial cycle monitor enable Constant value of 0. The special cycle monitor is alwaysdisabled.4R/WMemory write and invalidate enable Default value of 0. It enables Memory Write and InvalidCommand generation.0: Memory write must be used1: The µPD72873, when acts as PCI master, can generate the command5RVGATM color palette invalidate enable Constant value of 0. VGA color palette invalidate isalways disabled.6R/WParity error response Default value of 0. It defines if the µPD72873 responds to PERR.0: Ignore parity error1: Respond to parity error78RR/WStepping enable Constant value of 0. Stepping is always disabled.System error enable Default value of 0. It defines if the µPD72873 responds to SERR.0: Disable system error checking1: Enable system error checking9RFast back-to-back enable Constant value of 0. Fast back-to-back transactions are onlyallowed to the same agent.15-10RReserved Constant value of 000000.20
Preliminary Data Sheet S15305EJ1V0DS
µPD728733.1.4 Offset_06 Status Register
This register tracks the status information of PCI-bus related events which are relevant to the µPD72873. “Read”and “Write” are handled somewhat differently.
Bits3-046,57R/WRRRRReserved Constant value of 0000.New capabilities Constant value of 1. It indicates the existence of the Capabilities List.Reserved Constant value of 00.Fast back-to-back capable Constant value of 1. It indicates that the µPD72873, as a target,cannot accept fast back-to-back transactions when the transactions are not to the same agent.8R/WSignaled parity error Default value of 0. It indicates the occurrence of any “Data Parity”.0: No parity detected (default)1: Parity detected10,9RDEVSEL timing Constant value of 01. These bits define the decode timing for DEVSEL.0: Fast (1 cycle)1: Medium (2 cycles)2: Slow (3 cycles)3: undefined11R/WSignaled target abort Default value of 0. This bit is set by a target device whenever itterminates a transaction with “Target Abort”.0: The µPD72873 did not terminate a transaction with Target Abort1: The µPD72873 has terminated a transaction with Target Abort12R/WReceived target abort Default value of 0. This bit is set by a master device whenever itstransaction is terminated with a “Target Abort”.0: The µPD72873 has not received a Target Abort1: The µPD72873 has received a Target Abort from a bus-master13R/WReceived master abort Default value of 0. This bit is set by a master device whenever itstransaction is terminated with “Master Abort”. The µPD72873 asserts “Master Abort” when atransaction response exceeds the time allocated in the latency timer field.0: Transaction was not terminated with a Master Abort1: Transaction has been terminated with a Master Abort14R/WSignaled system error Default value of 0. It indicates that the assertion of SERR by theDescriptionµPD72873.0: System error was not signaled1: System error was signaled15R/WReceived parity error Default value of 0. It indicates the occurrence of any PERR.0: No parity error was detected1: Parity error was detectedPreliminary Data Sheet S15305EJ1V0DS
21
µPD728733.1.5 Offset_08 Revision ID Register
This register specifies a revision number assigned by NEC Corporation for the µPD72873.
Bits7-0
R/WR
Description
Default value of 01H. It specifies the silicon revision. It will be incremented for subsequentsilicon revisions.
3.1.6 Offset_09 Class Code Register
This register identifies the class code, sub-class code, and programming interface of the µPD72873.
Bits7-015-823-16
R/WRRR
Description
Constant value of 10H. It specifies an IEEE1394 OHCI-compliant Host Controller.Constant value of 00H. It specifies an “IEEE1394” type.Constant value of 0CH. It specifies a “Serial Bus Controller”.
3.1.7 Offset_0C Cache Line Size Register
This register specifies the system cache line size, which is PC-host system dependent, in units of 32-bit words.The following cache line sizes are supported: 2, 4, 8, 16, 32, , and 128. All other values will be recognized as 0,i.e. cache disabled.
Bits7-0
R/WR/W
Default value of 00H.
Description
3.1.8 Offset_0D Latency Timer Register
This register defines the maximum amount of time that the µPD72873 is permitted to retain ownership of the busafter it has acquired bus ownership and initiated a subsequent transaction.
Bits7-0
R/WR/W
Description
Default value of 00H. It specifies the number of PCI-bus clocks that the µPD72873 may holdthe PCI bus as a bus-master.
3.1.9 Offset_0E Header Type Register
Bits7-0
R/WR
Description
Constant value of 00H. It specifies a single function device.
3.1.10 Offset_0F BIST Register
Bits7-0
R/WR
Description
Constant value of 00H. It specifies whether the device is capable of Built-in Self Test.
22
Preliminary Data Sheet S15305EJ1V0DS
µPD728733.1.11 Offset_10 Base Address 0 Register
This register specifies the base memory address for accessing all the “Operation registers” (i.e. control,configuration, and status registers) of the µPD72873, while the BIOS is expected to set this value during power-upreset.
Bits11-031-12
R/WRR/W
Description
Constant value of 000H. These bits are “read-only”.-
3.1.12 Offset_2C Subsystem Vendor ID Register
This register identifies the subsystem that contains the NEC’s µPD72873 function. While the ID is assigned by thePCI_SIG committee, the value should be loaded into the register from the external serial ROM after power-up reset.Access to this register through PCI-bus is prohibited.
Bits15-0
R/WR
Default value of 1033H.
Description
3.1.13 Offset_2E Subsystem ID Register
This register identifies the type of the subsystem that contains the NEC’s µPD72873 function. While the ID isassigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM afterpower-up reset. Access to this register through PCI-bus is prohibited.
Bits15-0
R/WR
Default value of 00E7H.
Description
3.1.14 Offset_34 Cap_Ptr Register
This register points to a linked list of additional capabilities specific to the µPD72873, the NEC’s implementation ofthe 1394 OHCI specification.
Bits7-0
R/WR
Description
Constant value of 60H. The value represents an offset into the µPD72873’s PCI ConfigurationSpace for the location of the first item in the New Capabilities Linked List.
3.1.15 Offset_3C Interrupt Line Register
This register provides the interrupt line routing information specific to the µPD72873, the NEC’s implementation ofthe 1394 OHCI specification.
Bits7-0
R/WR/W
Description
Default value of 00H. It specifies which input of the host system interrupt controller theinterrupt pin of the µPD72873 is connected to.
Preliminary Data Sheet S15305EJ1V0DS
23
µPD728733.1.16 Offset_3D Interrupt Pin Register
This register provides the interrupt line routing information specific to the µPD72873, the NEC’s implementation ofthe 1394 OHCI specification.
Bits7-0R/WRDescription Constant value of 01H. It specifies PCI INTA is used for interrupting the host system.3.1.17 Offset_3E Min_Gnt Register
This register specifies how long of a burst period the µPD72873 needs, assuming a clock rate of 33 MHz.Resolution is in units of ¼ µs. The value should be loaded into the register from the external serial EEPROM uponpower-up reset, and access to this register through PCI-bus is prohibited.
Bits7-0
R/WR
Description
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.18 Offset_3F Max_Lat Register
This register specifies how often the µPD72873 needs to gain access to the PCI-bus, assuming a clock rate of 33MHz. Resolution is in units of ¼ µs. The value should be loaded into the register from the external serial EEPROMafter hardware reset, and access to this register through PCI-bus is prohibited.
Bits7-0
R/WR
Description
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.19 Offset_40 PCI_OHCI_Control Register
This register specifies the control bits that are IEEE1394 OHCI specific. Vendor options are not allowed in thisregister. It is reserved for OHCI use only.
Bits0
R/WR/W
Description
PCI global SWAP Default value of 0. When this bit is 1, all quadrates read from and written tothe PCI Interface are byte swapped, thus a “PCI Global Swap”. PCI addresses for expansionROM and PCI Configuration registers, are, however, unaffected by this bit. This bit is notrequired for motherboard implementations.
31-1
R
Reserved Constant value of all 0.
3.1.20 Offset_60 Cap_ID & Next_Item_Ptr Register
The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while theNext_Item_Ptr describes the location of the next item in the µPD72873’s Capability List.
Bits7-0
R/WR
Description
Cap_ID Constant value of 01H. The default value identified the Link List item as being the PCIPower Management registers, while the ID value is assigned by the PCI SIG.
15-8
R
Next_Item_Ptr Constant value of 00H. It indicated that there are no more items in the LinkList.
24
Preliminary Data Sheet S15305EJ1V0DS
µPD728733.1.21 Offset_62 Power Management Capabilities Register
This is a 16-bit read-only register that provides information on the power management capabilities of theµPD72873.
Bits2-0R/WRDescriptionVersion Constant value of 010. The power management registers are implemented asdefined in revision 1.1 of PCI Bus Power Management Interface Specification.3458-6RRRRPME clock Constant value of 0.Reserved Constant value of 0.DSI Constant value of 0.Auxiliary Power Default value of 000. This field reports the Vaux power requirements for theµPD72873. This data is programable from EEPROM. 111 – 375 mA maximum current required for a 3.3 Vaux, 110 – 320 mA maximum current required for a 3.3 Vaux, 101 – 270 mA maximum current required for a 3.3 Vaux, 100 – 220 mA maximum current required for a 3.3 Vaux, 011 – 160 mA maximum current required for a 3.3 Vaux, 010 – 100 mA maximum current required for a 3.3 Vaux, 001 – 55 mA maximum current required for a 3.3 Vaux, 000 – 0 (self powered)91015-11RRRD1_support Constant value of 1. The µPD72873 supports the D1 Power Management state.D2_support Constant value of 1. The µPD72873 supports the D2 Power Management state.PME_supportD3SUP = ‘High’ : Constant value of 11111.D3SUP = ‘Low’ : Constant value of 01111.This field indicates the power states in which the µPD72873 may assert PME. A value of “0” forany bit indicates that the function is not capable of asserting the PME signal while in that powerstate. bit (11) – PME_D0. PME can be asserted from D0. bit (12) – PME_D1. PME can be asserted from D1. bit (13) – PME_D2. PME can be asserted from D2. bit (14) – PME_D3hot. PME can be asserted from D3hot. bit (15) – PME_D3cold. PME can be asserted from D3cold.Preliminary Data Sheet S15305EJ1V0DS
25
µPD728733.1.22 Offset_ Power Management Control/Status Register
This is a 16-bit register that provides control status information of the µPD72873.
Bits1,0
R/WR/W
Description
PowerState Default value is undefined. This field is used both to determine the current powerstate of the µPD72873 and to set the µPD72873 into a new power state.
00: D0 (DMA contexts: ON, Link Layer: ON, PME will be asserted upon INTA being active)01: D1 (DMA contexts: OFF, Link Layer: ON, PME will be asserted upon INTA being active)10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon
LinkON being active)
11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon
LinkON being active)
The LPS is a PHY/Link interface signal and is defined in P1394a-2000. It is an internal signal inthe µPD72873.
7-28
RR/W
Reserved Constant value of 000000.
PME_En Default value of 0. This field is used to enable the specific power managementfeatures of the µPD72873.
12-914,1315
RRR/W
Data_Select Constant value of 0000.Data_Scale Constant value of 00.
PME_Status Default value is undefined. A write of ‘1’ clears this bit, while a write of ‘0’ isignored.
26
Preliminary Data Sheet S15305EJ1V0DS
µPD728733.2 CardBus Mode Configuration Register (CARD_ON = High)
31
24
23
16
15
08
07
00
Device IDVendor ID00HStatus
Command
04H
Class Code
Revision ID
08HBIST
Header Type
Latency Timer
Cache Line Size
0CHBase Address 0
10HBase Address 1 (Cardbus Status Reg) Note14HBase Address 2 (Cardbus Status Reg)
Note
18HReserved1CHReserved20HReserved
24HCardbus CIS Pointer Note
28HSubsystem ID
Subsystem Vendor ID
2CHReserved
30HReserved
Cap_Ptr
34HReserved
38HMax_Lat
Min_Gnt
Interrupt Pin
Interrupt Line3CHPCI_OHCI_Control
40HReserved44HReserved48HReserved4CHReserved50HReservedHReserved58HReserved
5CHPower Management Capabilities
Next_Item_Ptr
Cap_ID60HReserved
Power Management Control/Status
HReserved68HReserved6CHReserved70HReserved74HReserved78HReserved7CHCIS Area Note
80HFCH
Note Different from PCI Bus Mode Configuration Register.
Preliminary Data Sheet S15305EJ1V0DS
27
µPD728733.2.1 Offset_14/18 Base Address 1/2 Register (Cardbus Status Registers)
Bits7-031-8
R/WRR/W
Constant value of 00.-Description
(1) Function Event Register (FER) (Base Address 1 (2) + 0H)
Bits0
R/WR
Write Protect (No Use).Read only as ‘0’
1
R
Ready Status (No Use).Read only as ‘0’
2
R
Battery Voltage Detect 2 (No Use).Read only as ‘0’
3
R
Battery Voltage Detect 1 (No Use).Read only as ‘0’
414-51531-16
R/WRR/WR
General Wake Up
Reserved. Read only as ‘0’Interrupt
Reserved. Read only as ‘0’
Description
(2) Function Event Mask Register (FEMR) (Base Address 1 (2) + 4H)
Bits0
R/WR
Write Protect (No Use).Read only as ‘0’
1
R
Ready Status (No Use).Read only as ‘0’
2
R
Battery Voltage Detect 2 (No Use).Read only as ‘0’
3
R
Battery Voltage Detect 1 (No Use).Read only as ‘0’
45613-7141531-16
R/WRRRR/WR/WR
General Wake Up MaskBAM. Read only as ‘0’PWM. Read only as ‘0’Reserved. Read only as ‘0’Wake Up MaskInterrupt
Reserved. Read only as ‘0’
Description
28
Preliminary Data Sheet S15305EJ1V0DS
µPD72873(3) Function Reset Status Register (FRSR) (Base Address 1 (2) + 8H)
Bits0
R/WR
Write Protect (No Use).Read only as ‘0’
1
R
Ready Status (No Use).Read only as ‘0’
2
R
Battery Voltage Detect 2 (No Use).Read only as ‘0’
3
R
Battery Voltage Detect 1 (No Use).Read only as ‘0’
414-51531-16
R/WRR/WR
General Wake Up MaskReserved. Read only as ‘0’Interrupt
Reserved. Read only as ‘0’
Description
(4) Function Force Event Register (FFER) (Base Address 1 (2) + CH)
Bits0
R/WR
Write Protect (No Use).Read only as ‘0’
1
R
Ready Status (No Use).Read only as ‘0’
2
R
Battery Voltage Detect 2 (No Use).Read only as ‘0’
3
R
Battery Voltage Detect 1 (No Use).Read only as ‘0’
414-51531-16
R/W-R/WR
General Wake Up MaskNo UseInterrupt
Reserved. Read only as ‘0’
Description
3.2.2 Offset_28 Cardbus CIS Pointer
This register specifies start memory address of the Cardbus CIS Area.
Bits31-0
R/WR
Starting Pointer of CIS Area.Constant value of 00000080H.
Description
3.2.3 Offset_80 CIS Area
The µPD72873 supports external Serial ROM (AT24C02 compatible) interface.
CIS Area Register can be loaded from external Serial ROM in the CIS area when CARD_ON is 1.
Preliminary Data Sheet S15305EJ1V0DS
29
µPD728734. PHY FUNCTION4.1 Cable Interface
4.1.1 Connections
Figure 4-1. Cable Interface
Connection Detection CurrentConnection Detection ComparatorCommon Mode Speed Current driver+-DriverTpBiasTpAp7 kΩ7 kΩTpAn56 Ω56 Ω56 Ω56 ΩTpBp7 kΩ7 kΩTpBnReceiver+-Arbitration Comparators+-+-Common Mode Comparator+-Connection Detection CurrentConnection Detection ComparatorDriverReceiver+-Arbitration Comparators+-+-Common Mode Comparators+-+-1 µF0.01 µF5.1 kΩ270 pFCommon Mode Speed Current DriverTpBiasTpBpDriver7 kΩ7 kΩTpBnReceiver+-Arbitration Comparators+-+-Common Mode Comparator+-270 pF5.1 kΩ
0.01 µF1 µF56 Ω56 Ω56 Ω56 ΩTpAp7 kΩ7 kΩTpAn+-DriverReceiver+-Arbitration Comparators+-+-Common Mode Comparators+-+-30
Preliminary Data Sheet S15305EJ1V0DS
µPD728734.1.2 Cable Interface Circuit
Each port is configured with two twisted-pairs of TpA and TpB.
TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables.
During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller isencoded, converted from parallel to serial and transmitted.
While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallelafter synchronization by SCLK Note, then transmitted to the Link layer controller in 2/4/8 bits according to the data rateof 100/200/400 Mbps.
The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state ofthe 1394 bus is transmitted to the state machine in the LSI.
Note The SCLK is a PHY/Link interface signal and is defined in P1394a-2000. It is an internal signal in the
µPD72873.4.1.3 CPS
Connect an external resistor of 390 kΩ between the CPS pin and the power cable, and an external resistor of 100kΩ between the CPS pin and the GND to monitor the power of the power cable.
If the cable power falls under 7.5 V there is an indication to the Link layer that the power has failed.4.1.4 Unused Ports
TpAp, TpAn : Not connectedTpBp, TpBn : AGNDTpBias : Not connected
4.2 PLL and Crystal Oscillation Circuit
4.2.1 Crystal Oscillation Circuit
To supply the clock of 24.576 MHz ± 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm.4.2.2 PLL
The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz).
4.3 PC0 to PC2
The PC0 to PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Referto Section 4.3.4.1 of the IEEE1394-1995 specification for information regarding the Pwr_class. The value of Pwr canbe changed with software through the Link layer; this pin sets the initial value during Power-on Reset. Use a pull-upor pull-down resistor of 1 kΩ based on the application.
4.4 P_RESET
Connect an external capacitor of 0.1 µF between the pins P_RESET and GND. If the voltage drops below 0 V, areset pulse is generated. All of the circuits are initialized, including the contents of the PHY register.
4.5 RI0, RI1
Connect an external resistor of 9.1 kΩ ± 0.5 % to limit the LSI’s current.
Preliminary Data Sheet S15305EJ1V0DS
31
µPD728735. ELECTRICAL SPECIFICATIONSAbsolute Maximum Ratings
Parameter
Power supply voltageInput voltage
SymbolVDDVI
LVTTL @ (VI < 0.5 V + VDD)PCI @ (VI < 3.0 V + VDD)
Output voltage
VO
LVTTL @ (VO < 0.5 V + VDD)PCI @ (VO < 3.0 V + VDD)
Operating ambient temperatureStorage temperature
TATstg
Condition
Rating–0.5 to +4.6–0.5 to +4.6–0.5 to +6.6–0.5 to +4.6–0.5 to +6.60 to +70–65 to +150
UnitVVVVV°C°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on theverge of suffering physical damage, and therefore the product must be used under conditions thatensure that the absolute maximum ratings are not exceeded.
Recommended Operating Ranges
Parameter
Power supply voltage
SymbolVDD
Condition
Used to clamp reflection on PCI bus.
Rating4.5 to 5.53.0 to 3.6
Operating ambient temperature
TA
0 to +70
UnitVV°C
32
Preliminary Data Sheet S15305EJ1V0DS
µPD72873DC Characteristics (VDD = 3.3 V ± 10 %, VSS = 0 V, TA = 0 to +70°C)
Parameter
High-level input voltageLow-level input voltageHigh-level output currentLow-level output currentInput leakage currentPCI interface
High-level input voltageLow-level input voltageHigh-level output currentLow-level output currentInput leakage currentCable interfaceDifferential input voltage
VID
Cable input, 100 Mbps operationCable input, 200 Mbps operationCable input, 400 Mbps operationTpB common mode input voltage
VICM
100 Mbps speed signaling off200 Mbps speed signaling400 Mbps speed signaling
Differential output voltageTpA common mode output voltage
VODVOCM
Cable output (Test load 55Ω)100 Mbps speed signaling off200 Mbps speed signaling400 Mbps speed signaling
TpA common mode output current
ICM
100 Mbps speed signaling off200 Mbps speed signaling400 Mbps speed signaling
Power status threshold voltageTpBias output voltage
VTHVTPBIAS
CPS
1.6651421321181.1650.9350.523172.01.6651.4381.030–0.81–4.84–12.40
2602602602.5152.5152.515265.02.0152.0152.015+0.44–2.53–8.107.52.015
mVmVmVVVVmVVVVmAmAmAVV
VIHVILIOHIOLIL
VOH = 2.4 VVOL = 0.4 VVIN = VDD or GND
2.0–0.5–29
±10.05.5+0.8
VVmAmA
SymbolVIHVILIOHIOLIL
VOH = 2.4 V,
GROM_SDA, GROM_SCLVOL = 0.4 V,
GROM_SDA, GROM_SCL
ConditionMIN.2.0–0.5–66
TYP.MAX.VDD+0.5+0.8
UnitVVmAmA
VIN = VDD or GND±10.0µA
µA
Remarks 1. Digital core runs at 3.3 V.
2. PCI Interface can run at 5 or 3.3 V, depending on the choice of 5 V-PCI or 3.3 V-PCI.3. All other I/Os are 3.3 V driving, and 5 V tolerant.4. 5 V are used only for 5 V-PCI clamping diode.
5.0 V3.3 V
Protection CircuitI/O Buffer
Preliminary Data Sheet S15305EJ1V0DS
33
µPD72873AC Characteristics
PCI Interface
See PCI local bus specification Revision 2.2.Serial ROM Interface
See AT24C01A/02/04/08/16 Spec. Sheet.
34
Preliminary Data Sheet S15305EJ1V0DS
6. PACKAGE DRAWING
120-PIN PLASTIC TQFP (FINE PITCH) (14x14)AB90619160CD12013031FGHIMJPKSNSLMNOTEEach lead centerline is located within 0.09 mm ofits true position (T.P.) at maximum material condition.Preliminary Data Sheet S15305EJ1V0DS
µPD72873detail of lead endSQRITEMMILLIMETERSA16.0±0.2B14.0±0.2C14.0±0.2D16.0±0.2F1.2G1.2H0.18±0.05I0.09J0.4 (T.P.)K1.0±0.2L0.5±0.2M0.145±0.05N0.08P1.0±0.1Q0.1±0.05R3°+−73°°S1.2 MAX.S120GC-40-9EV-135
µPD728737. RECOMMENDED SOLDERING CONDITIONS
The µPD72873 should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device MountingTechnology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC salesrepresentative.
Table 7-1. Surface Mounting Type Soldering Conditions
µPD72873GC-9EV: 120-pin plastic TQFP (Fine pitch) (14 x 14)SolderingMethodInfrared reflow
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher).Count: three times or less
Exposure limit: 3 daysNote (after that prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C Max., Time: 3 sec. Max. (per pin row)
—
Soldering Conditions
RecommendedCondition SymbolIR35-103-3
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
36
Preliminary Data Sheet S15305EJ1V0DS
µPD72873Preliminary Data Sheet S15305EJ1V0DS
37
[MEMO]
[MEMO]
38
µPD72873Preliminary Data Sheet S15305EJ1V0DS
µPD72873NOTES FOR CMOS DEVICES1PRECAUTION AGAINST ESD FOR SEMICONDUCTORSNote:Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide andultimately degrade the device operation. Steps must be taken to stop generation of static electricityas much as possible, and quickly dissipate it once, when it has occurred. Environmental controlmust be adequate. When it is dry, humidifier should be used. It is recommended to avoid usinginsulators that easily build static electricity. Semiconductor devices must be stored and transportedin an anti-static container, static shielding bag or conductive material. All test and measurementtools including work bench and floor should be grounded. The operator should be grounded usingwrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions needto be taken for PW boards with semiconductor devices on it.2HANDLING OF UNUSED INPUT PINS FOR CMOSNote:No connection for CMOS device inputs can be cause of malfunction. If no connection is providedto the input pins, it is possible that an internal input level may be generated due to noise, etc., hencecausing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levelsof CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unusedpin should be connected to VDD or GND with a resistor, if it is considered to have a possibility ofbeing an output pin. All handling related to the unused pins must be judged device by device andrelated specifications governing the devices.3STATUS BEFORE INITIALIZATION OF MOS DEVICESNote:Power-on does not necessarily define initial status of MOS device. Production process of MOSdoes not define the initial operation status of the device. Immediately after the power source isturned ON, the devices with reset function have not yet been initialized. Hence, power-on doesnot guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until thereset signal is received. Reset operation must be executed immediately after power-on for deviceshaving reset function.Preliminary Data Sheet S15305EJ1V0DS
39
µPD72873EEPROM and Firewarden are trademarks of NEC Corporation.VGA is a trademark of IBM Corporation.
•The information in this document is current as of August, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information.•No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.•NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.•Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.•While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features.•NEC semiconductor products are classified into the following three quality grades:\"Standard\developed based on a customer-designated \"quality assurance program\" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. \"Standard\":Computers, office equipment, communications equipment, test and measurement equipment, audioand visual equipment, home electronic appliances, machine tools, personal electronic equipmentand industrial robots\"Special\":Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disastersystems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support)\"Specific\":Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, lifesupport systems and medical equipment for life support, etc.The quality grade of NEC semiconductor products is \"Standard\" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application.(Note)(1)\"NEC\" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.(2)\"NEC semiconductor products\" means any semiconductor product developed or manufactured by or forNEC (as defined above).M8E 00. 4
因篇幅问题不能全部显示，请点此查看更多更全内容
Copyright © 2019- oldu.cn 版权所有 浙ICP备2024123271号-1
违法及侵权请联系：TEL:199 1889 7713 E-MAIL:2724546146@qq.com
本站由北京市万商天勤律师事务所王兴未律师提供法律服务