Introduction to LVDS, PECL, and CML

Application Note:

HFAN-1.0

Rev 1; 4/08

Introduction to LVDS, PECL, and CML

[Some parts of this application note first appeared in Electronic Engineering Times on July 3, 2000, Issue 1120.]

Maxim Integrated Products

Table of Contents

1 2

Introduction........................................................................................................................................................1 PECL Interface...................................................................................................................................................1 2.1 PECL Output Structure...................................................................................................................................1 2.2 PECL Input Structure.....................................................................................................................................2 3

CML Interface....................................................................................................................................................3 3.1 CML Output Structure....................................................................................................................................3 3.2 CML Input Structure......................................................................................................................................3 4 LVDS Interface..................................................................................................................................................4 4.1 LVDS Output Structure..................................................................................................................................4 4.2 LVDS Input Structure.....................................................................................................................................4 5 Mutual Interfaces................................................................................................................................................6 5.1 CML to CML..................................................................................................................................................6 5.2 PECL to PECL...............................................................................................................................................6 5.2.1 DC-Coupling: Thèvenin Equivalent of 50Ω to (VCC-2V)......................................................................6 5.2.2 AC-Coupling..........................................................................................................................................7 5.3 LVDS to LVDS Interface...............................................................................................................................8 6

Interface between LVDS, PECL, and CML.......................................................................................................8 6.1 LVPECL to CML...........................................................................................................................................8 6.1.1 AC-Coupling..........................................................................................................................................8 6.1.2 DC-Coupling..........................................................................................................................................9 6.2 CML to LVPECL.........................................................................................................................................11 6.3 LVPECL to LVDS.......................................................................................................................................11 6.3.1 DC-Coupling........................................................................................................................................11 6.3.2 AC-Coupling........................................................................................................................................11 6.4 LVDS to LVPECL.......................................................................................................................................11 6.4.1 DC-Coupling........................................................................................................................................11 6.4.2 AC-Coupling........................................................................................................................................13 6.5 CML and LVDS Interfacing.........................................................................................................................14

Application Note HFAN-1.0 (Rev.1, 4/08) Maxim Integrated Products

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List of Figures

Figure 1. PECL output structure.................................................................................................................................1 Figure 2. PECL input structure...................................................................................................................................2 Figure 3. CML output structure..................................................................................................................................3 Figure 4. CML output waveform for DC- and AC-coupling......................................................................................3 Figure 5. CML input circuit configuration.................................................................................................................3 Figure 6. LVDS output structure................................................................................................................................4 Figure 7. LVDS input structure..................................................................................................................................4 Figure 8. CML to CML interface...............................................................................................................................6 Figure 9. Thevenin equivalent transformation...........................................................................................................6 Figure 10. DC-coupling between PECL and PECL...................................................................................................7 Figure 11. AC-coupling between PECL and PECL...................................................................................................7 Figure 12. LVDS to LVDS interface..........................................................................................................................8 Figure 13. AC-coupling between LVPECL and CML...............................................................................................8 Figure 14. Resistor network between LVPECL and CML (MAX3875)....................................................................9 Figure 15. DC-coupling between LVPECL and CML (MAX3875)..........................................................................9 Figure 16. AC-coupling between CML and LVPECL.............................................................................................10 Figure 17. DC-coupling between LVPECL and LVDS...........................................................................................10 Figure 18. AC-coupling between LVPECL and LVDS...........................................................................................11 Figure 19. DC-coupling between LVDS and LVPECL...........................................................................................12 Figure 20. AC-coupling between LVDS and LVPECL...........................................................................................13 Figure 21. AC-coupling between CML and LVDS..................................................................................................14 Figure 22. AC-coupling between LVDS and CML..................................................................................................14

Application Note HFAN-1.0 (Rev.1, 4/08) Maxim Integrated Products

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LVDS, PECL, and CML I/O Structures

1 Introduction

As the demand for high-speed data transmission grows, the interface between high-speed ICs becomes critical in achieving high performance, low power, and good noise immunity. Three commonly used interfaces are PECL (positive-referenced emitter-coupled logic), LVDS (low-voltage differential signals), and CML (current mode logic). When designing high-speed systems, people often encounter the problem of how to connect different ICs with different interfaces. To deal with this, it is important to understand the input and output circuit configurations of each interface for proper biasing and termination. This paper describes various ways of interconnecting between PECL, CML, and LVDS for high-speed communication systems, using Maxim products as examples.

serial and parallel data links. First developed by Motorola, the PECL standard has long since gained popularity with the rest of the electronics industry.

2.1 PECL Output Structure

The PECL output structure is shown in Figure 1. It consists of a differential pair that drives a pair of emitter followers. The output emitter followers should operate in the active region, with DC current flowing at all times. This increases switching speeds and helps maintain fast turn-off times. The proper termination for a PECL output is 50Ω to (VCC–2V). At this termination, both OUT+ and OUT- will typically be (VCC−1.3V), resulting in a DC current flow of approximately 14mA. The PECL output impedance is low, typically on the order of (4-5)Ω, which provides superior driving capability. When PECL outputs drive a transmission line, this low output impedance, which generates a mismatch in back termination, can result in high-frequency aberrations.

2 PECL Interface

PECL originates from ECL but uses a positive power supply. The relatively small swing of the PECL signal makes this logic suitable for high-speed

VCCOUT+OUT- 50Ω 50ΩVCC-2.0V PECL Termination

Figure 1. PECL output structure

Application Note HFAN-1.0 (Rev.1, 4/08) Maxim Integrated Products

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2.2 PECL Input Structure

The PECL input structure is shown in Figure 2. It is a current switching differential with high input impedance. In order to provide operating headroom, the common-mode voltage should be around (VCC-1.3V). Maxim’s HF communication products have two types of PECL input circuit configurations. One is with on-chip biasing (i.e., MAX3885); the other is without on-chip biasing (i.e., MAX3867, MAX3675). In the latter case, it is required that proper DC biasing be provided externally.

Table I gives Maxim’s PECL input and output specifications.

VCCThe PECL interface is suitable for both +5.0V and +3.3V power supplies. When the power supply is +3.3V, it is commonly referred to as low-voltage PECL (LVPECL).

Careful attention must be paid to power-supply de-coupling in order to keep the power-supply rail noise free. Also, the AC and DC requirements of the PECL outputs place additional constraints on termination networks.

VCCVCC-1.3V 1kΩ1kΩIN+

IN+

IN-

IN-

(a) With on-chip high-impedance biasing (b) Without on-chip biasing

Figure 2. PECL input structure

Table I. PECL Input and Output Specifications PARAMETER Output High Voltage Output Low Voltage

Input High Voltage Input Low Voltage

CONDITIONS TA = 0°C to +85°C TA = –40°C TA = 0°C to +85°C TA = –40°C

MIN VCC – 1.025 VCC – 1.085 VCC – 1.81 VCC – 1.83 VCC – 1.16 VCC – 1.81 TYP MAX VCC – 0.88 VCC – 0.88 VCC – 1.62 VCC – 1.55 VCC – 0.88 VCC – 1.48 UNITS V V V V V V Application Note HFAN-1.0 (Rev.1, 4/08) Maxim Integrated Products

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OUT+VCCVCC-0.2VVCC-0.4V3 CML Interface

CML is among the simplest protocols for high-speed interfacing. On-chip input and output terminations minimize the number of external components required to set the operating conditions. The signal swing provided by the CML output is small, resulting in low power consumption. In addition, the 50Ω back termination minimizes the back reflection, thus reducing high-frequency aberrations.

(a) DC-Coupled with 50Ω to VCCOUT+VCC-0.2VVCC-0.4VVCC-0.6V3.1 CML Output Structure

The CML output consists of a differential pair with 50Ω collector resistors, as shown in Figure 3. The signal swing is supplied by switching the current in a common-emitter differential pair. Assuming the current source is 16mA typical, and the CML output is loaded with a 50Ω pullup to VCC, then the single-ended CML output voltage swings from VCC to (VCC−0.4V). In this case the CML output differential swing is 800mV typical and the common mode voltage is (VCC – 0.2V). For the same source current, if the CML output is AC-coupled to 50Ω, the DC impedance is now set by the 50Ω collector resistor. The CML output common-mode voltage is now (VCC – 0.4V), and the differential swing is 800mVp-p. The output waveforms for AC- and DC-coupling are shown in Figure 4.

VCC(b) AC-Coupled to 50Ω termination

Figure 4. CML output waveform for DC- and AC-coupling

3.2 CML Input Structure

The CML input structure has several features that make it a popular choice for high-speed operations. As shown in Figure 5, Maxim’s CML input structure has 50Ω input impedance for easy termination. The input transistors are emitter followers that drive a differential-pair amplifier.

Figure 5. CML input circuit configuration

VCC50Ω50ΩOUT+OUT-

50Ω50ΩIN+

16mAIN-

Figure 3. CML output structure

Table II lists the CML output and input specifications for the MAX3831/MAX3832.

Application Note HFAN-1.0 (Rev.1, 4/08)

Maxim Integrated Products

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Table II. CML Input and Output Specifications (Load = 50Ω to VCC)

PARAMETER

Differential Output Voltage Output Common Mode Voltage Single-Ended Input Voltage Range Differential Input Voltage Swing

CONDITION

VIS

MIN 0 VCC – 0.6V

400

TYP 800 VCC-0.2

MAX 1000 VCC + 0.2V 1200

Units mVp-p V V mVp-p

Note: Different Maxim products have different CML input sensitivities (i.e., MAX3875, MAX3876).

4 LVDS Interface

LVDS is defined for low-voltage differential signal point-to-point transmission. It has several advantages that make it attractive to users. The low signal swing yields low power consumption, at most 4mA are sent through the 100Ω termination resistor. This makes LVDS desirable for parallel link data transmission. The signal levels are low enough in voltage to allow for supply voltages as low as 2.5V. Because the input voltage range is from 0V to 2.4V and the single-ended signal swing is 400mV, the input common-mode voltage will be from 0.2V to 2.2V. Therefore, LVDS can tolerate a ±1V ground potential difference between the LVDS driver and receiver.

4.1 LVDS Output Structure

Maxim’s LVDS output structures are optimized for low-power and high-speed operation. The circuit configuration is shown in Figure 6. The differential output impedance is typically 100Ω. Refer to Table III for other output specifications.

4.2 LVDS Input Structure

The LVDS input structure, shown in Figure 7, has on-chip 100Ω differential impedance between IN+ and IN-. To accommodate a wide common-mode voltage range, an adaptive level-shifting circuit sets the common-mode voltage to a constant value at the input of a Schmitt trigger. The Schmitt trigger provides hysteresis relative to the input threshold. This signal is then applied to the following differential amplifier stage.

Figure 6. LVDS output structure

Application Note HFAN-1.0 (Rev.1, 4/08)

VCCOUT+OUT-

Figure 7. LVDS input structure

IN+

50ΩADAPTIVELEVELSCHIMITTSHIFTERTRIGGER50Ω IN-Table III summarizes Maxim’s LVDS input and output specifications. (Applies to the MAX3831, MAX3832, and MAX30.)

Maxim Integrated Products

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Table III. LVDS Input and Output Specifications PARAMETER Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output for Complementary States Offset Output Voltage Change in Magnitude of Output Offset Voltage for Complementary States Differential Output Impedance Output Current Output Current Input Voltage Range Differential Input Voltage Input Common-Mode Current

Vi 󰂨Vid󰂨 ∆󰂨Vos󰂨

SYMBOL CONDITION VOH VOL 󰂨Vod󰂨 ∆󰂨Vod󰂨

MIN 0.925 250

TYP

MAX 1.475 400 25

UNITS V V mV mV

1.125

1.275 25

V mV

Short together Short to GND

LVDS Input VOS = 1.2V

80 0 100

350

120 12 40 2.4

Ω mA mA V mV µA

Threshold Hysteresis Differential Input Impedance

Rin

85

70 100

115

mV Ω

Application Note HFAN-1.0 (Rev.1, 4/08) Maxim Integrated Products

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5 Mutual Interfaces

5.1 CML to CML

If the receiver and transmitter use the same supply voltage for VCC, the CML driver output can be DC-coupled to the CML receiver input without additional components. AC-coupling can be used for systems in which the receiver and transmitter are at different supply voltages. For AC-coupling, the coupling capacitor should be large enough to avoid excessive low-frequency droop when the data signal contains long strings of consecutive identical digits (refer to application note HFAN-1.1). The CML to CML connection is given in Figure 8.

5.2 PECL to PECL

5.2.1 DC-Coupling: Thèvenin Equivalent of 50Ω

to (VCC-2V) The PECL output is designed to drive a 50Ω load to (VCC – 2V). Because the potential of (VCC – 2V) is usually not available for termination networks, it is often preferable to find a parallel combination of resistors that result in a Thèvenin equivalent circuit. Figure 9 shows the result of the Thèvenin transformation. The termination requirement of 50Ω to (VCC – 2V) imposes the conditions of

(V−2V)=V󰂧R2󰂷

CC

CC󰂨󰂩R1+R2󰂸󰂹

and (R1//R2)=50Ω.

Solving for R1 and R2 yields the following

R1=

50⋅VCC

(V−2V)

and R2=25⋅VCC

CC

Application Note HFAN-1.0 (Rev.1, 4/08)

CML CML DRIVER

RECEIVER(a) DC-coupling between CML and CML

CML CML DRIVER RECEIVER(b) AC-coupling between CML and CML Figure 8. CML to CML interface

PECLPECLDRIVER RECEIVER50Ω50ΩVCC - 2V

VCC

R1R1

PECL PECL DRIVER

RECEIVERR2R2

Figure 9. Thevenin equivalent transformation

Maxim Integrated Products

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At 3.3V, the standard 5% resistor values would be R1 = 130Ω and R2 = 82Ω. At +5.0V, the derived values would be R1 = 82Ω and R2 = 130Ω. Figure 10 gives the Thevenin equivalent termination networks for +3.3V suppy and +5.0V supply. Note that PECL output configurations are open-emitter and have no back termination (see Figure 1). 5.2.2 AC-Coupling

When PECL outputs need to be AC-coupled to a 50Ω termination, a resistor to ground should be used to DC-bias the PECL output before AC-coupling to the transmission line, as shown in Figure 11. For a PECL input termination R2 and R3 should be selected by considering the following: (1) PECL input DC bias voltage should be set at (Vcc-1.3V); (2) matching the characteristic impedance of the transmission line; (3) power consumption; and (4) external component count. Fig. 11(a) optimizes for the lowest number of components. In this case R2 and R3 are determined by

R3⋅Vcc

R2+R3

=Vcc−1.3V,

and R2//R3≈50Ω. This results in:

R2 = 82Ω and R3 = 130Ω for +3.3V supply

and

R2 = 68Ω and R3 = 180Ω for +5.0V supply

VCC

R1

R2R2PECLDRIVER

PECLRECEIVERR1

R3R3

(a)

Figure 11. AC-coupling between PECL and PECL

Application Note HFAN-1.0 (Rev.1, 4/08) +3.3V

130Ω130Ω

PECL PECL DRIVER

RECEIVER82Ω82Ω

(a) 3.3V supply

+5.0V

82Ω82Ω

PECL PECL DRIVER RECEIVER130Ω130Ω

(b) 5.0V supply

Figure 10. DC-coupling between PECL and PECL

VCCR1R2R2PECLDRIVER100ΩPECLRECEIVERR1R3R3(b)Maxim Integrated Products

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The disadvantage of Figure 11(a) is that the power consumption caused by this termination network is high. For systems where power consumption is a main concern, Figure 11 (b) can be used. In this case we need to make

R3⋅Vcc

R2+R3

=Vcc−1.3V, and

R2//R3//50Ω=50Ω.

One solution is this R2 = 2.7kΩ and R3 = 4.3kΩ for +3.3V supply

and

R2 = 2.7kΩ and R3 = 7.8kΩ

for +5.0V supply

Because the PECL output common-mode voltage is fixed at (VCC-1.3V), the DC-biasing resistor (R1) can be selected by assuming a 14mA DC current. An initial calculation would be R1=(Vcc−1.3V)/14mA, resulting in R1=142Ω for +3.3V supply and R1=270Ω for +5.0V supply. However, this calculation gives less than 50Ω AC termination resistance as seen from the PECL output. In real applications to balance both the AC and DC requirements, R1 can be selected between 142Ω and 200Ω for a +3.3V supply and between 270Ω and 350Ω for a +5.0V supply.

Further improvement in PECL terminations can be achieved in two ways: (1) Add a resistor in series with the coupling capacitor such that the AC impedance seen by the PECL driver is close to 50Ω, (2) place an inductor in series with R1, which allows the AC impedance to be dominated by the receiver impedance and not by R1.

5.3 LVDS to LVDS Interface

Because the LVDS input has on-chip terminations, the interface between LVDS driver to LVDS receiver is simply a direct connection, as shown in Figure 12.

LVDS LVDS DRIVER RECEIVER

Figure 12. LVDS to LVDS interface

Application Note HFAN-1.0 (Rev.1, 4/08)

6 Interface between LVDS, PECL,

and CML

In the following, +3.3V PECL is assumed.

6.1 LVPECL to CML

LVPECL to CML coupling can be accomplished using AC or DC methods. 6.1.1 AC-Coupling

One way to AC-couple an LVPECL driver to a CML receiver is shown in Figure 13. On each of the LVPECL outputs, a resistor R (142Ω to 200Ω) can be connected to ground for proper DC biasing. If the LVPECL differential output swing is larger than what the CML receiver can handle, a 25Ω series resistor can be used to provide a voltage attenuation of 0.67.

R

25Ω

LVPECL CMLDRIVER

RECEIVER25ΩR

Figure 13. AC-coupling between LVPECL and CML

Maxim Integrated Products

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6.1.2 DC-Coupling

To perform DC-coupling between LVPECL and CML, a level shift network is needed to meet the common-mode voltage requirement at both the LVPECL output and the CML input. The attenuation introduced by this level shift network must be small so that the signal swing at the input of the CML receiver is above the receiver sensitivity. In addition, the total impedance seen from the LVPECL output should be kept close to 50Ω for impedance matching. The following example shows how to use an LVPECL output to drive the MAX3875 CML input. In this case the level shift network can be built as shown in Figure 14.

+3.3VR150ΩAR3LVPECL

BR2 MAX3875

Figure 14. Resistor network between LVPECL and CML (MAX3875)

The following conditions need to be met:

VA=VCC−2.0V=

R2⋅Vcc

R2+R1//(R3+50Ω)

(1) [Open circuit Thevenin equivalent voltage]

Zin=R1//R2//(R3+50Ω)=50Ω

(2) [Thevenin equivalent resistance]

V⋅R3+50Ω⋅(Vcc−1.3V)

B=VCC−0.2V=

Vcc(50Ω+R3)

(3) [Assuming VA = VPECL-CM = (VCC-1.3V)]

Gain=

50

(R3+50)

≥0.042

(4)

(Note: Assuming the LVPECL output minimum differential swing is 1200mV, and the MAX3875 has a input sensitivity of 50mV, the gain should be greater than 50mV/1200mV = 0.042.)

Application Note HFAN-1.0 (Rev.1, 4/08)

By solving the above equations, we obtained R1 = 182Ω, R2 = 82.5Ω, and R3 = 294Ω (standard 1% values). The resulting VA = 1.35V, VB = 3.11V, gain = 0.147, and Zin = 49Ω. When Connecting the LVPECL output to the MAX3875 input through this network, the measured VA = 2.0V and VB = 3.13V. The DC-coupling between LVPECL and MAX3875 is shown in Figure 15. For other CML inputs, the minimum input common-mode voltage and minimum input swing can be different; therefore, the user can derive different resistor values based on the above considerations.

+3.3V

182Ω182Ω

290Ω

LVPECLCMLDRIVER RECEIVER290Ω

82Ω

82Ω

Figure 15. DC-coupling between LVPECL and CML (MAX3875)

Maxim Integrated Products

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+3.3V+3.3V2.7kΩ2.7kΩ 82Ω 82ΩCMLDRIVER100ΩLVPECL RECEIVERCMLDRIVERLVPECL RECEIVER4.3kΩ4.3kΩ130Ω130Ω(a)(b) CML DRIVER

100Ω

LVPECL RECEIVER

(c) LVPECL with on-chip high-impedance biasing Figure 16. AC-coupling between CML and LVPECL

R1LVPECL

AVCC +3.3V R1

R2

LVPECLDRIVER

LVDS RECEIVERR3

R2BLVDSR2

R350Ω

Virtual (AC) Ground R1+3.3V

R3

(a) Single-ended equivalent circuit (b) LVPECL to LVDS interface

Figure 17. DC-coupling between LVPECL and LVDS

Application Note HFAN-1.0 (Rev.1, 4/08) Maxim Integrated Products

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6.2 CML to LVPECL

AC-coupling is required when interfacing from CML to LVPECL (see Figure 16).

6.3 LVPECL to LVDS

6.3.1 DC-Coupling

DC-coupling between LVPECL and LVDS requires a level shifting/attenuation network, shown in Figure 17. Several conditions must be considered. First, the LVPECL output is optimized for a 50Ω load to (VCC-2V). Next, the network attenuation should be such that the LVPECL output signal after attenuation is within the LVDS input range. Note that the LVDS input impedance is 100Ω differential, or 50Ω to virtual ground on each line (Figure 7). This does not contribute to the DC termination impedance, but does contribute to the AC termination impedance. This means that the AC and DC impedance will always be different. Therefore, the following equations should be satisfied:

VA=VCC−2V=V2+R3

CC⋅

RR1+R2+R3

(1) RAC=R1//(R2+(R3//50Ω)=50Ω (2) RDC=R1//(R2+R3)≈50Ω (3) Gain=R3//50Ω

R2+(R3//50Ω)

≥0.17

(4)

By letting VCC = +3.3V and solving the above equations, we obtain R1 = 182Ω, R2 = 47.5Ω, and R3 = 47.5Ω. The calculated VA = 1.13V, RAC = 51.5Ω, RDC = 62.4Ω, and gain = 0.337. When connecting the LVPECL output through this termination network to the LVDS input, the measured common-mode voltages are VA = 2.1V and VB = 1.06V. Assuming the minimum LVPECL differential output is 930mV, then the minimum voltage applied to the LVDS input is 313mV, which meets the LVDS input sensitivity requirement. On the another hand, if the maximum LVPECL differential output is 1.9V, then the maximum signal at the LVDS input is 0mV, which also meets the LVDS input specifications.

Application Note HFAN-1.0 (Rev.1, 4/08)

6.3.2 AC-Coupling

The AC-coupling solution between LVPECL and LVDS is shown in Figure 18. The LVPECL output is DC-biased through a resistor R (142Ω to 200Ω) to ground. A 50Ω series resistor is necessary to attenuate the LVPECL output signal to satisfy the LVDS input requirement. At the LVDS input, a 5.0kΩ resistor to ground on each side is used to bias the common-mode voltage.

R5kΩ

50Ω

LVPECLLVDSDRIVER

50Ω

RECEIVER R5kΩ

Figure 18. AC-coupling between LVPECL and LVDS

6.4 LVDS to LVPECL

A number of considerations should be made when using DC- and AC-coupling of LVDS to LVPECL 6.4.1 DC-Coupling

When DC-coupling between LVDS and LVPECL, use the resistor network shown in Figure 19. This resistor network shifts the DC level from the LVDS output (1.2V) to the LVPECL input (Vcc-1.3V). Because the LVDS output voltage is referenced to ground and the LVPECL input voltage is referenced to Vcc, this level shift network should be built so that the LVDS output is not sensitive to power-supply variations. Another important consideration is to make a trade-off between power consumption and speed. If we choose lower resistor values for (R1, R2, R3), the time constant formed by this resistor network and the LVPECL input parasitic capacitance is small, allowing for high-speed operation. On the other hand the total power consumption will be increased because more current will flow through these resistors. In this case the LVDS output performance can be affected due to power-supply variations. Again, the impedance

Maxim Integrated Products

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matching and network attenuation should be considered. The resistor values can be derived from the following equations:

By applying VCC = +3.3V and solving the equations above, we choose R1 = 374Ω, R2 = 249Ω, and R3 = 402Ω. This results in VA = 1.2V, VB = 2.0V, and RIN = 49Ω, and gain = 0.62. Because the minimum LVDS output is 500mVP-P differential, the signal swing at the LVPECL input becomes 310mV P-P. This voltage swing might be small for the PECL input standard, but most of the Maxim LVPECL input can accept this signal swing because of the high input amplifier gain. In a real application, the user needs to make a decision based on performance requirements.

VA=Vcc⋅(VB=Vcc⋅(

R1

)=1.2V

R1+R2+R3

(1) (2) (3)

R1+R2

)=Vcc−1.3V

R1+R2+R3

RIN=(

R3⋅(R1+R2)

)//62Ω=50Ω

R3+(R1+R2)

R3

Gain=

(R2+R3)

(4)

+3.3V +3.3V

R1

R2

R3

R3 B LVPECL

R2 LVDS DRIVER

124Ω

R2

R1

+3.3V

R3

LVPECL RECEIVERLVDS A R1 124/2 Ω

Virtual (AC) Ground

(a) LVDS to LVPECL interface (b) Single-ended equivalent circuit

Figure 19. DC-coupling between LVDS and LVPECL

Application Note HFAN-1.0 (Rev.1, 4/08) Maxim Integrated Products

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6.4.2 AC-Coupling

The AC-coupling between LVDS and LVPECL is simple, and two examples are given in Figure 20.

LVDSDRIVER100ΩLVPECL RECEIVER

(a) LVPECL with on-chip termination (MAX3885)

+3.3V+3.3V

2.7kΩ2.7kΩ

82Ω 82Ω

LVDS DRIVER

100Ω

LVPECL RECEIVERLVDS DRIVERLVPECL RECEIVER4.3kΩ4.3kΩ

130Ω130Ω

(b) LVPECL without on-chip termination (MAX3867)

Figure 20. AC-coupling between LVDS and LVPECL

Application Note HFAN-1.0 (Rev.1, 4/08)

Maxim Integrated Products

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6.5 CML and LVDS Interfacing

Use AC-coupling when interfacing between CML and LVDS (Figure 21). Note that the CML output signal swing should be within the range that the LVDS input can handle.

If an LVDS driver needs to drive a CML receiver, the AC-coupling solution is given in Figure 22.

5kΩ

CML LVDSDRIVER RECEIVER5kΩ

Figure 21. AC-coupling between CML and LVDS

LVDS CMLDRIVER RECEIVER

Figure 22. AC-coupling between LVDS and CML

Application Note HFAN-1.0 (Rev.1, 4/08) Maxim Integrated Products

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