HIGH PERFORMANCE CURRENT MODE PWM CONTROLLERNOT FOR NEW DESIGN
1
■
■
■
■
■
■
FEATURES
TRIMMED OSCILLATOR DISCHARGE CURRENT
CURRENT MODE OPERATION TO 500kHz AUTOMATIC FEED FORWARD COMPENSATION
LATCHING PWM FOR CYCLE-BY-CYCLE CURRENT LIMITING
INTERNALLY TRIMMED REFERENCE WITH UNDERVOLTAGE LOCKOUT
HIGH CURRENT TOTEM POLE OUTPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS
LOW START-UP CURRENT (< 0.5mA) DOUBLE PULSE SUPPRESSION
Figure 1. Package
DIP-8SO-8Table 1. Order Codes
Part Number
UC2842AD1; UC3842AD1;UC2843AD1; UC3843AD1;UC2844AD1; UC3844AD1;UC2845AD1; UC3845AD1UC2842AN; UC3842AN;UC2843AN; UC3843AN;UC2844AN; UC3844AN;UC2845AN; UC3845AN
PackageSO-8
DIP-8
2DESCRIPTION
The UC384xA family of control ICs provides thenecessary features to implement off-line or DC toDC fixed frequency current mode control schemeswith a minimal external parts count. Internally im-plemented circuits include a trimmed oscillator forprecise DUTY CYCLE CONTROL under voltagelockout featuring start-up current less than 0.5mA,a precision reference trimmed for accuracy at theerror amp input, logic to insure latched operation,a PWM comparator which also provides currentlimit control, and a totem pole output stage de-signed to source or sink high peak current. Theoutput stage, suitable for driving N-Channel MOS-FETs, is low in the off-state.
Differences between members of this family arethe under-voltage lockout thresholds and maxi-mum duty cycle ranges. The UC3842A andUC3844A have UVLO thresholds of 16V (on) and10V (off), ideally suited off-line applications Thecorresponding thresholds for the UC3843A andUC3845A are 8.5 V and 7.9V. The UC3842A andUC3843A can operate to duty cycles approaching100%. A range of the zero to < 50 % is obtained bythe UC3844A and UC3845A by the addition of aninternal toggle flip flop which blanks the output offevery other clock cycle.
Figure 2. Block Diagram (toggle flip flop used only in UC3844A and UC3845A)
Vi734VGROUND5UVLOS/R5VREFINTERNALBIASVREF GOODLOGICRT/CT4OSC+-ERROR AMP.2RR1VSRCURRENTSENSECOMPARATORD95IN3318VREF5V 50mA2.50V6TOUTPUTVFBCOMPCURRENTSENSE213PWMLATCHMay 2004
REV. 51/16
UC384XA - UC284XA
Table 2. Absolute Maximum Ratings
SymbolViViIOEOSupply Voltage (Ii < 30mA)Output Current
Output Energy (capacitive load)Analog Inputs (pins 2, 3)
Error Amplifier Output Sink Current
PtotPtotTstgTJTLPower Dissipation at Tamb ≤ 25 °C (DIP-8)Power Dissipation at Tamb ≤ 25 °C (SO-8)Storage Temperature RangeJunction Operating TemperatureLead Temperature (soldering 10s)
Parameter
Supply Voltage (low impedance source)
Value30Self Limiting
±15– 0.3 to 5.5
101.25800– 65 to 150– 40 to 150
300
AµJVmAWmW°C°C°CUnitV
* All voltages are with respect to pin 5, all currents are positive into the specified terminal.
Figure 3. DIP-8/SO-8 Pin Connection (Top view)
COMPVFBISENSERT/CT1234D95IN3328765VREFViOUTPUTGROUNDTable 3. Pin Description
N°12345678
PinCOMPVFBISENSERT/CTGROUNDOUTPUTVCCVrefFunction
This pin is the Error Amplifier output and is made available for loop compensation.
This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider.
A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction.
The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible.This pin is the combined control circuitry and power ground.
This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin.
This pin is the positive supply of the control IC.
This is the reference output. It provides charging current for capacitor CT through resistor RT.
2/16
UC384XA - UC284XA
Table 4. Thermal Data
SymbolRth j-ambParameter
Thermal Resistance Junction-ambient
Max.
DIP-8100
SO-8150
Unit°C/W
Table 5. Electrical Characteristcs
( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA;0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
Symbol
Parameter
Test Condition Tj = 25°C Io= 1mA12V ≤ Vi ≤ 25V1 ≤ Io ≤ 20mA(Note 2)
Line, Load, Temperature10Hz ≤ f ≤ 10KHzTj = 25°C (note 2)
Tamb
UC284XAMin. Typ.4.95
5.00230.2
4.9
505
-30
-100520.251.68.32.50-0.1650.7602-0.55
9017012-16.20.8
1.125-180571––8.82.55-1
650.7602-0.55-3047–––7.8
5.1Max.5.052025
UC384XAMin. Typ.4.90
5.00230.2
4.82
505-100520.251.68.32.50-0.19017012-16.20.8
1.125-180571––8.82.58-25.18Max.5.102025
Unit
REFERENCE SECTIONVREF∆VREF∆VREFOutput VoltageLine RegulationLoad RegulationTotal Output Variation
eNOutput Noise VoltageLong Term Stability
VmVmVmV/°CVµVmVmAKHz%%VmAVµAdBMHzdBmAmAVV
∆VREF/∆TTemperature Stability
= 125°C, 1000Hrs
(note 2)
ISC
fOSCOutput Short CircuitFrequency
Tj = 25°CVCC = 12V to 25VTA = Tlow to Thigh(peak to peak)TJ = 25°CVPIN1 = 2.5VVFB = 5V2V ≤ Vo ≤ 4VTJ = 25°C12V ≤ Vi ≤25VVPIN2 = 2.7VVPIN1= 1.1V
VPIN2 = 2.3V VPIN1 = 5VVPIN2 = 2.3V;RL = 15KΩ to Ground
VPIN2 = 2.7V;RL = 15KΩ to Pin 8(note 3 & 4)VPIN1 = 5V (note 3)12 ≤ Vi ≤ 25V (note 3)
OSCILLATOR SECTION
47–––7.82.45
∆fOSC/∆VFrequency Change with Volt.∆VREF/∆TFrequency Change with Temp.VOSCIdischgV2IbBWPSRRIoIoOscillator Voltage SwingDischarge Current (VOSC =2V)Input VoltageInput Bias CurrentAVOLUnity Gain BandwidthPower Supply Rejec. RatioOutput Sink CurrentOutput Source CurrentVOUT HighVOUT Low
CURRENT SENSE SECTIONGVV3SVRIbGain
Maximum Input SignalSupply Voltage RejectionInput Bias CurrentDelay to Output
2.850.9
3170-2150
-103003.151.1
2.850.9
3170-2150
-103003.151.1
V/VVdBµAns
ERROR AMP SECTION
2.42
3/16
UC384XA - UC284XA
Table 5. Electrical Characteristcs (continued)
( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA;0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
Symbol
Parameter
Test Condition
UC284XAMin. Typ.0.11.6
1312
13.513.50.75050
1.2150150Max.0.42.2
1312
UC384XAMin. Typ.0.11.613.513.50.75050
1.2150150Max.0.42.2
Unit
OUTPUT SECTIONVOLVOHVOLStrtfOutput Low LevelOutput High LevelUVLO SaturationRise TimeFall Time
ISINK = 20mAISINK = 200mAISOURCE = 20mAISOURCE = 200mAVCC = 6V; ISINK = 1mA Tj = 25°CCL = 1nF (2)Tj = 25°CCL = 1nF (2)UNDER-VOLTAGE LOCKOUT SECTION
Start ThresholdMin Operating Voltage
After Turn-on
PWM SECTION
Maximum Duty CycleMinimum Duty Cycle
TOTAL STANDBY CURRENT
IstStart-up Current
Vi = 6.5V for UCX843A/45A
Vi = 14V for UCX842A/44A
IiVizOperating Supply CurrentZener Voltage
VPIN2 = VPIN3 = 0VIi=25mA
30
0.30.31236
0.50.517
30
0.30.31236
0.50.517
mAmAmAV
X842A/3AX844A/5A
9447
98
100500
9447
98
100500
%%%
X842A/4AX843A/5AX842A/4A
157.
168.410
179.011
14.57.88.5
168.410
17.59.011.5
VVVnsVVVVVns
Notes:1.Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close
to Tamb as possible.
2.These parameters, although guaranteed, are not 100% tested in production.3.Parameter measured at trip point of latch with VPIN2 = 0.4.Gain defined as : A = ∆VPIN1/∆VPIN3; 0 ≤ VPIN3 ≤ 0.8V5.Adjust Vi above the start threshold before setting at 15 V.
4/16
UC384XA - UC284XA
Figure 4. Open Loop Test Circuit.
VREF4.7KΩ2N2222100KΩERROR AMP.ADJUST4.7KΩCOMPVFB1KΩISENSEADJUST5KΩISENSERT/CTRTVREF123465CTD95IN343A80.1µF7Vi0.1µFOUTPUTGROUND1W1KΩViOUTPUTGROUNDHigh peak currents associated with capacitive loads necessitate careful grounding techniques. Timing andbypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 KΩpotentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.Figure 5. Oscillator Frequency vs Timing
Resistance
fo(Hz)D96IN362Figure 7. Oscillator Discharge Current vs.
Temperature.
Idischg(mA)D95IN335Vi=15VVOSC=2V1MCT=4708.51nFpF100K2.2nF8.04.7nF10K7.51K3001K3K10K30KRT(Ω)7.0-55-250255075100TA(˚C)Figure 6. Maximum Duty Cycle vs Timing
Resistor
fo(Hz)D96IN363Figure 8. Error Amp Open-Loop Gain and
Phase vs. Frequency.
(dB)80D95IN33780Gain60Vi=15VVO=2V to 4VRL=100KTA=25˚Cφ306090120150604040Phase200-20102003001K3K10K30KRT(Ω)1001K10K100K1M180f(Hz)5/16
UC384XA - UC284XA
Figure 9. Current Sense Input Threshold vs.
Error Amp Output Voltage.
Vth(V)1.0D95IN338Figure 12. Output Saturation Voltage vs. Load
Current.
Vsat(V)D95IN341Vi=15VTA=25˚CVi-1-2Source Saturation(Load to Ground)TA=25˚CTA=-40˚C0.8TA=125˚C0.60.40.20.032Vi=15V80µs Pulsed Load 120Hz RateTA=-40˚CTA=25˚CSink Saturation(Load to Vi)0200400600TA=-40˚C10GNDIO(mA)0246VO(V)Figure 10. Reference Voltage Change vs.
Source Current..
60D95IN339Figure 13. Supply Current vs. Supply Voltage.
Ii(mA)20D95IN342Vi=15V5040TA=-40˚CTA=125˚C15RT=10KCT=3.3nFVFB=0VISense=0VTA=25˚C30TA=25˚CUCX843/4520100020406010580100Iref(mA)0010UCX842/442030Vi(V)Figure 11. Reference Short Circuit Current vs.
Temperature..
ISC(mA)1009080706050-55-250255075100TA(˚C)Vi=15VRL≤0.1ΩD95IN3406/16
UC384XA - UC284XA
Figure 14. Output Waveform.
Figure 15. Output Cross Conduction
Figure 16. Oscillator and Output Waveforms.
Vi78PWMRTCLOCK4IDCT5GNDD95IN344CT5V REGOUTPUT6OUTPUTLARGE RT/SMALL CTOSCILLATORCTOUTPUTSMALL RT/LARGE CTFigure 17. Error Amp Configuration.
2.5V1mA+ZiZfD95IN345VFBCOMP21-7/16
UC384XA - UC284XA
Figure 18. Under Voltage Lockout.
7ON/OFF COMMANDTO REST OF ICViICCUC3842AUC3843AUC3844AUC3845AVONVOFF16V10V8.4V7.6V<17mA<0.5mAVOFFVOND95IN346modVCCFigure 19. Current Sense Circuit.
ERRORAMPL.ISCOMPRRSCCURRENTSENSE5GND132RR1VCURRENTSENSECOMPARATORD95IN347Peak current (is) is determined by the formula1.0V
ISmax≈------------RS
A small RC filter may be required to suppress switch transients.Figure 20. Slope Compensation Techniques.
VREGRTISRSLOPER1RSRT/CTCTISENSE8VREGRT84ISRSLOPERT/CTCTISENSE435GNDRSR135GNDD95IN3488/16
UC384XA - UC284XA
Figure 21. Isolated MOSFET Drive and Current Transformer Sensing.
VCC7Vin5.0Vref+-ISOLATIONBOUNDARYVGS Waveforms+-SR-+COMP/LATCHQ6Q1+0-50% DC+0-25% DCIpk =V(pin 1) -1.43RS(N)NSP3CD95IN349RRSNSNPFigure 22. Latched Shutdown.
4OSC8RBIASR+1mA+212N39052N39035-EA2RRD95IN350SCR must be selected for a holding current of less than 0.5mA at TA(min).The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.9/16
UC384XA - UC284XA
Figure 23. Error Amplifier Compensation
From VORi2RdCfRf152.5V+-EA+1mA2RRError Amp compensation circuit for stabilizing any current-mode topology exceptfor boost and flyback converters operating with continuous inductor current.+1mARPRi2CPRdCfRf15D95IN351From VO2.5V+-EA2RRError Amp compensation circuit for stabilizing current-mode boost and flybacktopologies operating with continuous inductor current.Figure 24. External Clock Synchronization.
VREF8RBIASRT4CTEXTERNALSYNC INPUT0.01µF47Ω215+-EA+ROSC2RRThe diode clamp is required if the Sync amplitude is large enough to causethe bottom side of CT to go more than 300mV below groundD95IN35210/16
UC384XA - UC284XA
Figure 25. External Duty Cycle Clamp and Multi Unit Synchronization.
VREFRA8+-5K2C5K1+-S43Q72+-EA2R4+8RBIASROSCRB655KRR5NE5551f =1.44(RA + 2RB)CDmax =RBRA + 2RBTO ADDITIONALUCX84XAsD95IN353Figure 26. Soft-Start Circuit
8RBIASR4+1mA21MΩ1C5+-EA2RROSC5Vref+-S+1V-QRD95IN311/16
UC384XA - UC284XA
Figure 27. Soft-Start and Error Amplifier Output Duty Cycle Clamp.
VCCVin78RBIASR4+1mA2R215CR1BC109VCLAMP = ·R1R1 + R2where 0 UC384XA - UC284XA Figure 28. SO-8 Mechanical Data & Package Dimensions mmDIM.MIN.AA1A2BCD (1)EeHhLkddd5.800.250.401.350.101.100.330.194.803.801.276.200.501.270.2280.0100.016TYP.MAX.1.750.251.650.510.255.004.00MIN.0.0530.0040.0430.0130.0070.10.150.0500.2440.0200.050TYP.MAX.0.0690.0100.0650.0200.0100.1970.157inchOUTLINE ANDMECHANICAL DATA0˚ (min.), 8˚ (max.)0.100.004Note:(1)Dimensions D does not include mold flash, protru-sions or gate burrs.Mold flash, potrusions or gate burrs shall not exceed0.15mm (.006inch) in total (both side).SO-80016023 C13/16 UC384XA - UC284XA Figure 29. DIP-8 Mechanical Data & Package Dimensions mmDIM.MIN.Aa1Bbb1DEee3e4FILZ3.187.952.7.627.626.65.083.811.520.1250.511.150.3560.2041.650.550.30410.929.750.3130.1000.3000.3000.2600.2000.1500.060TYP.3.320.0200.0450.0140.0080.0650.0220.0120.4300.384MAX.MIN.TYP.0.131MAX.inchOUTLINEANDMECHANICALDATADIP-814/16 UC384XA - UC284XA Table 6. Revision History DateMarch 1999May 2004 Revision 45 First Issue in EDOCSNOT FOR NEW DESIGN Description of Changes 15/16 UC384XA - UC284XA Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grantedby implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subjectto change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are notauthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics.All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 16/16 因篇幅问题不能全部显示,请点此查看更多更全内容
Copyright © 2019- oldu.cn 版权所有 浙ICP备2024123271号-1
违法及侵权请联系:TEL:199 1889 7713 E-MAIL:2724546146@qq.com
本站由北京市万商天勤律师事务所王兴未律师提供法律服务