FPGA可编程逻辑器件芯片5CGXBC5C7F27C8N中文规格书

Memory Modes

Memory Modes

ArriaII memory blocks allow you to implement fully synchronous SRAM memory in multiple modes of operation. M9K and M144K blocks do not support asynchronous memory (unregistered inputs). MLABs support asynchronous (flow-through) read operations.

Depending on which memory block you target, you can use the following modes:

■■■■■■

“Single-Port RAM Mode” on page3–10“Simple Dual-Port Mode” on page3–12“True Dual-Port Mode” on page3–15“Shift-Register Mode” on page3–17“ROM Mode” on page3–18“FIFO Mode” on page3–18

1

To choose the desired read-during-write behavior, set the read-during-write behavior to either new data, old data, or don't care in the RAM MegaWizard Plug-In Manager in the Quartus II software. For more information about this behavior, refer to “Read-During-Write Behavior” on page3–21.

When using the memory blocks in ROM, single-port, simple dual-port, or true

dual-port mode, you can corrupt the memory contents if you violate the setup or hold time on any of the memory block input registers. This applies to both read and write operations.

1

Single-Port RAM Mode

All memory blocks support single-port mode. Single-port mode allows you to do either a one-read or a one-write operation at a time. Simultaneous reads and writes are not supported in single-port mode. Figure3–9 shows the single-port RAM configuration.

Figure3–9.Single-Port Memory (Note1)

data[ ]address[ ]wrenbyteena[]addressstall inclockclockenardenaclrNote to Figure3–9:

(1)You can implement two single-port memory blocks in a single M9K and M144K blocks. For more information, refer

to “Packed Mode Support” on page3–5.

q[]outclockArria II Device Handbook Volume 1: Device Interfaces and Integration

Chapter 3:Memory Blocks in Arria II DevicesMemory Features

Table3–3 lists the truth table for the ECC status flags.Table3–3.Truth Table for ECC Status Flags in Arria II Devices

Status

No error

Single error and fixedDouble error and no fixIllegalIllegalIllegalIllegal

eccstatus[2]

0010011

eccstatus[1]

0100101

eccstatus[0]

011100X

11

You cannot use the byte enable feature when ECC is engaged.

Read-during-write old data mode is not supported when ECC is engaged. Figure3–8 shows a diagram of the ECC block of the M144K block.

Figure3–8.ECC Block Diagram of the M144K Block

8

Data Input

SECDED8Encoder

72

RAMArray

72

SECDEDEncoder

Comparator8

88

8

Error

Locator

ErrorCorrection Block

Data Output

FlagGenerator

3

Status Flags

Arria II Device Handbook Volume 1: Device Interfaces and Integration