元器件交易网www.cecb2b.com SLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER D3:21 Data Channel Expansion at up toDDDDDDDDDDDD D1.3 Gigabits per Second ThroughputSuited for Point-to-Point SubsystemCommunication With Very Low EMI3 Data Channels and Clock Low-VoltageDifferential Channels in and 21 Data andClock Low-Voltage TTL Channels OutOperates From a Single 3.3-V Supply and250 mW (Typ)5-V Tolerant SHTDN InputRising Clock Edge Triggered OutputsBus Pins Tolerate 4-kV HBM ESDPackaged in Thin Shrink Small-OutlinePackage With 20 Mil Terminal PitchConsumes <1 mW When DisabledWide Phase-Lock Input Frequency Range20 MHz to 67 MHzNo External Components Required for PLLInputs Meet or Exceed the Requirements ofANSI EIA/TIA-4 StandardIndustrial Temperature QualifiedTA = –40°C to 85°CReplacement for the DS90CR216DGG PACKAGE(TOP VIEW)descriptionD17D18GNDD19D20NCLVDSGNDA0MA0PA1MA1PLVDSVCCLVDSGNDA2MA2PCLKINMCLKINPLVDSGNDPLLGNDPLLVCCPLLGNDSHTDNCLKOUTD01234 56710111213141516171819202122232448474443424140393837363534333231302928272625VCCD16D15D14GNDD13VCCD12D11D10GNDD9VCCD8D7D6GNDD5D4D3VCCD2D1GNDThe SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shiftregisters, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a singleintegrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such asthe SN65LVDS95, over four balanced-pair conductors and expansion to 21 bits of single-ended LVTTLsynchronous data at a lower transfer rate.When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times theLVDS input clock (CLKIN). The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. Aphase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock forthe expanded data. The SN65LVDS96 presents valid data on the rising edge of the output clock (CLKOUT).The SN65LVDS96 requires only four line termination resistors for the differential inputs and little or no control.The data bus appears the same at the input to the transmitter and output of the receiver with data transmissiontransparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN)active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low levelon this signal clears all internal registers to a low level.The SN65LVDS96 is characterized for operation over ambient air temperatures of –40°C to 85°C.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 2000, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.comSLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER functional block diagram Serial-In/Parallel-OutShift RegisterA0PA0MSerial InCLKA,B, ...GD0D1D2D3D4D5D6Serial-In/Parallel-OutShift RegisterA1PA1MSerial InCLKA,B, ...GSerial-In/Parallel-OutShift RegisterA2PA2MSerial InCLKA,B, ...GD7D8D9D10D11D12D13Control LogicSHTDND14D15D16D17D18D19D207× Clock/PLLCLKCLKINPCLKINMClock InClock OutCLKOUT2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER CLKINPrevious CycleA0D0-1D6D5Current CycleD4D3D2D1D0D6+1Next CycleA1D7-1D13D12D11D10D9D8D7D13+1A2D14-1D20D19D18D17D16D15D14D20+1CLKOUTDnDn-1DnDn+1Figure 1. Typical ’LVDS96 Load and Shift Sequencesequivalent input and output schematic diagramsVCCVCCVCC300 kΩ300 kΩSHTDN50 Ω5 ΩD Output7 VAnPAnM7 V300 kΩ7 V7 VPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER absolute maximum ratings over operating free-air temperature (unless otherwise noted)†Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 VVoltage range at any terminal (except SHTDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 VVoltage range at SHTDN terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 VElectrostatic discharge (see Note 2):Bus pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 KVBus pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 VAll pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 KVAll pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 VContinuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table)Operating free-air temperature range, TA –40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 85°CStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.All voltage values are with respect to the GND terminals unless otherwise noted.2.This rating is measured using MIL-STD-883C Method, 3015.7.DISSIPATION RATING TABLEPACKAGEDGGTA ≤ 25°CPOWER RATING1316 mWDERATING FACTOR‡ABOVE TA = 25°C13.1 mW/°CTA = 70°CPOWER RATING724 mWTA = 85°CPOWER RATING526 mW‡This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.recommended operating conditionsMINSupply voltage, VCCHigh-level input voltage, VIHLow-level input voltage, VILMagnitude of differential input voltage, |VID|Common-mode input voltage, VICOperating free-air temperature, TA3SHTDNSHTDN0.120.80.62.4 NOM3.3MAX3.6UNITVVVVV°CŤVIDŤ2–40ŤVIDŤ852VCC–0.8timing requirementsPARAMETERStc§Input clock period§tc is defined as the mean duration of a minimum of 32,000 clock periods.MIN15.4NOMtcMAX50UNITns4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER TYP†electrical characteristics over recommended operating conditions (unless otherwise noted)PARAMETERVIT+VIT–VOHVOLPositive-going differential Input voltage thresholdNegative-going differential Input voltage threshold‡High-level output voltageLow-level output voltageIOH = –4 mAIOH = 4 mADisabled, all inputs openEnabled, AnP at 1 V and AnM at 1.4 V,tc = 15.38 nsEnabled, CL = 8 pF,Worst-case pattern (see Figure 4),tc = 15.38 nsHigh-level input current (SHTDN)Low-level input current (SHTDN)VIH = VCCVIL = 0 V60–1002.40.428082mA94±20±20µAµATEST CONDITIONSMINMAX100UNITmVmVVVµAICCQuiescentcurrent(average)Quiescent current (average)IIHIILIINInput current (A inputs)0 V ≤ VI ≤ 2.4 V±20µAIOZHigh-impedance output currentVO = 0 V to VCC±10µA†All typical values are VCC = 3.3 V, TA = 25°C.‡The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-goinginput voltage threshold only.switching characteristics over recommended operating conditions (unless otherwise noted)PARAMETERtsuthtRSKMtdData setup time, D0 through D20 toCLKOUT↑Data hold time, CLKOUT↑ to D0 throughD20Receiver inut skew margin§ Receiver input skew margin(see Figure 7)Delay time, input clock to output clock(see Figure 7)Change in outut clock eriod from cycleChange in output clock period from cycle#to cycleEnable time, SHTDN to phase lockDisable time, SHTDN to Off stateTEST CONDITIONSMIN4CL = 8 pF,=8pFSeeFigure5See Figure tc = 15.38 ns ((±0.2%),),|Input clock jitter| <50 ps¶tc = 15.38 ns (±0.2%)tc = 15.38 + 0.75 sin (2π500E3t) ±0.05 ns,See Figure 7tc = 15.38 + 0.75 sin (2π3E6t) ±0.05 ns,See Figure 7See Figure 8See FIgure 9TA = 0°C to 85°CTA = –40°C to 0°C4903503.7±80ps±3001400msns6800pspsnsTYP6nsMAXUNIT∆tC(O)tentdisttOutput transition time (10% to 90% tr or tf)CL = 8 pF3nstwOutput clock pulse duration0.43 tcns§tRSKM is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value of this parameter at clockperiods other than 15.38 ns can be calculated fromtc–600ps.14¶|Input clock jitter| is the magnitude of the change in the input clock period.#∆tC(O) is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.comSLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER PARAMETER MEASUREMENT INFORMATIONAPVID(VIAP + VIAM)/2VICVIAPVIAMAMFigure 2. Voltage DefinitionsCOMMON-MODE INPUT VOLTAGEvsDIFFERENTIAL INPUT VOLTAGE AND VCC2.5MAX at >3.15 VVIC– Common-Mode Input Voltage – VMAX at 3 V21.510.5MIN000.10.20.30.40.50.6|VID|– Differential Input Voltage and VCC – VFigure 3. Maximum VIC versus VID and VCC6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER PARAMETER MEASUREMENT INFORMATIONTCLKIN/CLKOUTEVEN DnODD DnFigure 4. Worst-Case† Test Pattern†The worst-case test pattern produces nearly the maximum switching frequency for all of the LV-TTL outputs.tsuVOH2.4 VD0–270.4 VVOLthVOH2.4 V0.4 VVOLCLKOUTFigure 5. Setup and Hold-Time MeasurementsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•7元器件交易网www.cecb2b.comSLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER PARAMETER MEASUREMENT INFORMATIONTektronixHFS9003/HFS9DG1Stimulus System(Repeating Patterns1110111 and 0001000)AnDUTD0–D20Tektronix MicrowaveLogic Multi-BERT-100RXWord Error DetectorCLKINCLKOUTNOTES:A.CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs.B.The advance or delay is then reduced until there are no data errors observed.C.The magnitude of the advance or delay from step 2 is tRSKM.tc4/7 tc ± tRSKMts3/7 tc ± tRSKMAnand AnthCLKIN7×CLK(Internal)tdtwCLKOUTtr < 1 ns90%CLKIN or An10%tdtwCLKOUTVOH1.4 VVOL≅ 300 mV0 V≅ –300 mVFigure 6. Receiver Input Skew Margin, Setup/Hold Time, and td Definitions8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER PARAMETER MEASUREMENT INFORMATION+DeviceUnderTestReferenceΣ+VCOModulationv(t) = A sin(2πfmodt)HP8656B SignalGenerator,0.1 MHz–990 MHzRF OutputHP8665A SynthesizedSignal Generator,0.1 MHz–4200 MHzModulation InputOutputDevice UnderTestCLKINCLKOUTDTS2070CDigital TimeScopeInputFigure 7. Output Clock Jitter Test SetupCLKINAntenSHTDNDnInvalidValidFigure 8. Enable Time WaveformsCLKINtdisSHTDNCLKOUTFigure 9. Disable Time WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•9元器件交易网www.cecb2b.comSLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER TYPICAL CHARACTERISTICSWORST-CASE SUPPLY CURRENTvsFREQUENCY120100ICC– Supply Current – mAVCC = 3.6 V80VCC = 3 VVCC = 3.3 V604020030405060f – Frequency – MHz70Figure 1010POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER APPLICATION INFORMATION16-bit bus extensionIn a 16-bit bus application (Figure 11), TTL data and clock coming from bus transceivers that interface thebackplane bus arrive at the Tx parallel inputs of the LVDS serdestransmitter. The clock associated with the busis also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input. Thedata is then multiplexed into three different line drivers which perform the TTL to LVDS conversion. The clockis also converted to LVDS and presented to a separate driver. This synchronized LVDS data and clock at thereceiver, which recovers the LVDS data and clock, performs a conversion back to TTL. Data is thendemultiplexed into a parallel format. An on-chip PLL synchronizes the received clock with the parallel data, andthen all are presented to the parallel output port of the receiver.16-BitBTL BusInterfaceTTLInterfaceD0–D78LVDSInterface0 To 10 Meters(Media Dependent)SN65LVDS95SN65LVDS96TTLInterface816-BitBTL BusInterfaceSN74FB2032D0–D7SN74FB2032SN74FB2032D8–D1588D8–D15SN74FB2032CLKBackplaneBusXMIT ClockRCV ClockCLKBackplaneBusFigure 11. 16-Bit Bus Extension16-bit bus extension with parityIn the previous application we did not have a checking bit that would provide assurance that the data crossesthe link. If we add a parity bit to the previous example, we would have a diagram similar to the one in Figure12.The device following the SN74FB2032 is a low cost parity generator. Each transmit-side transceiver/paritygenerator takes the LVTTL data from the corresponding transceiver, performs a parity calculation over the byte,and then passes the bits with its calculated parity value on the parallel input of the LVDS serdes transmitter.Again, the on-chip PLL synchronizes this transmit clock with the eighteen parallel bits (16 data + 2 parity) at theinput. The synchronized LVDS data/parity and clock arrive at the receiver.The receiver performs the conversion from LVDS to LVTTL and the transceiver/parity generator performs theparity calculations. These devices compare their corresponding input bytes with the value received on the paritybit. The transceiver/parity generator will assert its parity error output if a mismatch is detected.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•11元器件交易网www.cecb2b.comSLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER APPLICATION INFORMATION16-BitBTL BusInterfaceTTLInterfaceTTLInterfaceW/ParityLVDSInterface0 To 10 Meters(Media Dependent)SN65LVDS95SN74FB2032D0–D7 Bit LatchableTransceiver/ WithParity GeneratorParitySN65LVDS968Parity9 Bit LatchableTransceiver/ WithParity GeneratorD0–D7SN74FB2032TTLInterfaceW/ParityTTLInterface16-BitBTL BusInterfaceD8–D15SN74FB2032 Bit LatchableTransceiver/ WithParity GeneratorParity8Parity9 Bit LatchableTransceiver/ WithParity GeneratorD8–D15SN74FB2032ParityErrorCLKBackplaneBusXMIT ClockRCV ClockCLKBackplaneBusFigure 12. 16-Bit Bus Extension With Paritylow cost virtual backplane transceiverFigure 13 represents LVDS serdes in an application as a virtual backplane transceiver (VBT). The concept ofa VBT can be achieved by implementing individual LVDS serdes chipsets in both directions of subsystemserialized links.Depending on the application, the designer will face varying choices when implementing a VBT. In addition tothe devices shown in Figure 13, functions such as parity and delay lines for control signals could be included.Using additional circuitry, half-duplex or full-duplex operation can be achieved by configuring the clock andcontrol lines properly.The designer may choose to implement an independent clock oscillator at each end of the link and then usea PLL to synchronize LVDS serdes’s parallel I/O to the backplane bus. Resynchronizing FIFOs may also berequired.BusTransceiversBackplaneBusBusTransceiversTTLInputsUp To21 or 28BitsLVDS SerdesTransmitterLVDSSerial Links4 or 5PairsLVDS SerdesTransmitterLVDS SerdesReceiverLVDS SerdesReceiverTTLOutputsUp To21 or 28BitsBusTransceiversBackplaneBusBusTransceiversFigure 13. Virtual Backplane Transceiver12POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SLLS296F – MAY 1998 – REVISED FEBRUARY 2000SN65LVDS96LVDS SERDES RECEIVER MECHANICAL DATADGG (R-PDSO-G**) 48 PIN SHOWNPLASTIC SMALL-OUTLINE PACKAGE0,50480,270,17250,08M6,206,008,307,900,15 NOMGage Plane0,250°–8°A0,750,50124Seating Plane1,20 MAX0,150,05PINS **DIMA MAX0,10485612,6014,1017,10A MIN12,4013,9016,904040078/F 12/97NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold protrusion not to exceed 0,15.Falls within JEDEC MO-153POST OFFICE BOX 655303 DALLAS, TEXAS 75265•13元器件交易网www.cecb2b.com
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