EDA英文练习习题册

Part one

1-1 Choices.（Choose the correct statement）

1.Large logical programmable devices can be cataloged as two types according to structure, which of the following is correct? _D___

A．FPGA and IP B．SOPC and CPLD C．GAL and CPLD D． FPGA and CPLD 2. According to the EDA design flowchart, which of the following sequence of simulating is correct? ____

①Timing Simulation ②Behavior simulation ③Logic simulation & synthesis ④Function simulationA．①②③④

B．②①④③

C．④③②①

D．②④③①

3. Which of the following is Embedded IP from ALTERA? __A__.

A.PicoBlaze,MicroBlaze/PowerPC 405 B. DSP C. PAC D. Nios/ARM 4. Which of the following description about the block diagram/schematic file is correct? _ A. Suitable to design large logical digital system design B.A design flowchart from bottom to top C. Functional Design D. Can’t describe hardware in different level in digital system design 5. Which of the following description about the process clause in VHDL is incorrect? ___ A. Process is a clause cycled foreverB. Process begins as the sensitive signal changing

C. Variable defined in the process can’t be used in other processD. Process includes description part, concurrent clauses and sensitive table

6. Which of the following description about signal and variable is incorrect? ______. A..Signal is a local data used only in the process B. Assignment in the process Validates immediatelyC. Scope of the signal is inter block &process D. Value Assignment with different symbol

7. Which of the following description about CPLD is correct? _____. A. XC9500 family devices from XILINX are CPLD

B. CPLD is abbreviation of field programmable generic array C. CPLD is early extended from FPGA D. CPLD is based on look out table (LUT)

8. Which of the following library is defined by current user?_____ A．IEEE library

B．VITAL library C．STD library D．WORK library

1

9. Which of the following number is correct?

A．10#1E8# B．16#E#E1 C．74HC124 D．X_16 10. Which of the following clause is not concurrent clause? ______ A．process clause B．case clause C．component clause

D．WHEN…ELSE…clause

11．Those who belong to the sequential logic circuit is (a) decoder (b) MUX (c) DFF (d) adder 12．Which of the following number is correct?

A．8#129# B．16#F#E1 C．74HC138 D．X_18 13．The expand name of text file in VHDL is (a) .gdf (b) .v (c) .vhd (d) .scf

14. Line note in VHDL begin with sign until end of the line。 (a) /* (b) // (c) -- (d) */

15. Among VHDL constant， High-impedance state is denoted by 。 (a) X (b) 1 (c) 0 (d) Z

16. Among VHDL constant，octal sign is denoted by 。 (a) b or B (b) d or D (c) o or O (d) h or H

17. the VHDL identifiers can be any sequence consisting of letter、 number and underline“_”，but the first character can not be 。

(a) capital letter (b) lowercase (c) number (d) underline“_”

18. The logical operation in VHDL，set A=”11010001”, B=”00011001”, then the result of expression “A and B” is 。

(a) “00010001” (b) “11011001” (c) “11001000” (d) “00110111” 19. In the following operation sign of VHDL，the priority of is the highest. (a) ** (b) + (c) * (d) /

20.the shift operation in VHDL，the sign“sll”is the for operation number。

(a) logical shift right (b) arithmetic shift right (c) logical shift left (d) arithmetic shift left

31. According to the EDA design flowchart, which of the following is correct? ____ ①Design Input ②Function simulation ③Synthesis ④Logic implementation

2

⑤Timing simulation ⑥Download ⑦Circuit debuggingA．①④③⑤⑥②⑦ B．①②③⑥⑤④⑦

C．①②③④⑤⑥⑦ D．①②④③⑥⑤⑦

32. Large logical programmable devices can be cataloged as two types according to structure, which of the following is correct? ____

A．FPGA and CPLD B．SOPC and CPLD C．GAL and CPLD D．FPGA and IP 33. Which of the following description about CPLD is correct? _____. A. CPLD is based on look out table (LUT) B. CPLD is based on ROM C. CPLD is based on PAL D. CPLD is based on GAL

34. Which of the following is Embedded IP from ALTERA? ____.

A.PicoBlaze,MicroBlaze/PowerPC 405 B. DSP C. PAC D. Nios/ARM 35. Which of the following description about the process clause in VHDL is incorrect? ___ A. Process is a clause cycled forever

B. Process begins as the sensitive signal changing

C. Variable defined in the process can’t be used in other process

D. Process includes description part, concurrent clauses and sensitive table 36. Which of the following description about rising edge is incorrect? ______. A.if clk'event and clk = '1' then B.if clk'stable and not clk = '1' then C.if rising edge(clk) then

D.if not clk'stable and clk = '1' then

37. Which of the following description about the block diagram/schematic file is correct? _ A. Suitable to design large logical digital system design B. Functional design C. A design flowchart from bottom to top

D. Can’t describe hardware in different level in digital system design 38. Which of the following library is defined by current user?_____ A．IEEE library

B．VITAL library C．STD library D．WORK library

39. Which of the following clause is not a concurrent clause? ______ A．process clause B．component clause C．case clause 40. Which of the following number is minimum?

3

D．WHEN…ELSE…clause

A. 2#1111_1110# B. 8#276# C. 10#170#

1-2 Explanation of the terms listed below bilingual.

D. 16#E#E1

ASIC CPLD EDA FPGA FSM HDL IP JTAG LPM PCB PLD RTL SOPC

Part two

2-1. Describe two basic types of digital design methodologies in VHDL 2-2. Give a brief description of the top-down design flow.

2-3. Give a brief description of the Design flow when using PLD/FPGA. 2-4. Give a brief description of the architecture of CPLD. 2-5. Give a brief description of the architecture of FPGA.

2-6. Give a brief description of the differences between CPLD and FPGA.

2-7.Description two basic design methods in EDA design

2-8.compare and explain three different description Styles of VHDL Digital Design

Part three

3-1．Fill in blank（填空题）

1. VHDL file type have 、 、 、 . 2. In graphic editor, the filename extension is ,which stands for graphic design file . 3. When using waveform editor, a file with extension stores the waveforms that will be used as simulation test vectors .

4. In text editor, the filename extension must be used for all files that contain VHDL code.

5. In text editor, the filename extension must be used for all files that contain VHDL code.

6.VHDL belongs to the following two types of language : and . 7.VHDL nine logic value states respectively are 、 、

、 、 etc.

8.In VHDL，the statement “If clk’even and clk=’1’”means the module event sprung by of clk.. 9.In port announcement statement of VHDL，the keyword is used to declare port as input direction.

4

10.In port announcement statement of VHDL, the keyword is used to declare port as bidirectional.

3-2. In the Expression below, how does B is expressed in the vhdl interior? (下式中，B在

VHDL内部是如何表示的？)

3-3. Computation of expression value (计算表达式的值) 3-4. Judgment expression value (判断表达式的值)

3-5.Explain the meaning of the following expression(说明下面表达式的含义)

3-6.Write completely vhdl language description for half adder with assign statement (写出半加器完整的语言描述,用赋值语句)。

3-7 Write completely vhdl language description for 8 bits register. 3-8. Write completely vhdl language description for 16 bits divider.

Part four

4-1．Given values of a, b as shown, write the result of expressions shown below.

（a、b、c的值在下面给出，写出下面表达式的值。） a=4’b0010，b=4’b1010

a&b=? a*b=? a**b=? a/b=? a+b=? -b=? nota=?

4-2．Memory indexing. A) Declare a 4K memory with word size of 8, and a 1-bit flag. B) Select the5th bit of the 12 word of the memory and put it in the flag. All the operations must be done as continuous assign statements.

（声明一个4k的存储器，每个单元的位宽是8bit；再声明一个1bit的标志信号；将存储器中第12单元第5bit的值赋给这个标志信号。所有的操作都用赋值来完成。）

th

4-3．Show values of x,y, and z in the first 100 ns of simulation.

(画出时序仿真时第一个100ns的x,y,z的波形。)

4-4．Write a VHDL description for a 4-bit adder-subtractor that adds when as is 1 and subtracts when as is 0.(编写一个4-bit加法器-减法器的VHDL描述，当as为1时相加，为0时相

减。)

4-5．What does the following code do？.(下面的代码实现了什么功能？)

If CLK’EVENT AND CLK=’1’ then

5

a<=b; b<=a;

end if

4-6．Write a negative edge trigger D-type flip-flop with an asynchronous active-low reset, a synchronous active-high set.

(编写一个具有异步低有效复位、同步高有效置位的下降沿触发的D触发器。)

4-7.Design a 110 sequence detector with VHDL code.

(用VHDL代码设计一个序列检测器，使其可以检测出110序列。)

4-8.Give the binary equivalent of these general format integers.

（写出下列数字的二进制形式。）

4-9.Design the given gate circuit in different description styles: structure description, behavior description and data flow description.

(分别用门级结构描述、数据流描述和行为描述三种方法实现下图所示的门电路。)

4-10．Design a 4-bit comparator which has two 4-bit inputs a and b and three outputs a_gt_b, a_eq_b and a_lt_b.

(设计一个4位比较器，该比较器有两个4bit输入a和b，输出大于、等于和小于三种比较结果。) 4-11．Design a 4-bit binary up-down counter. The counter has a synchronous rst input

and a parallel load enable, ld. If u_d is 1 count-up, and if it is 0 count-down is done. （设计一个4位二进制加减计数器。该计数器有一个同步输入rst和一个并行加载使能ld。如果u_d为1，则为加计数，如果为0，则为减计数。）

Part five

5-1. Behavioral specification of a full-adder 5-2. Gate level specification of a half-adder

5-3. structural specification of a 2-1 Multiplexer(门级结构描述的2 选1MUX)

5-4. Implement the logic for the multiplexer using basic logic gates, and give VHDL Description of 4-1 Multiplexer.

6

5-5. Data flow specification of a 4-1 Multiplexer(数据流方式描述的4 选1 MUX)

5-6. Behavioral specification of a 2-1 Multiplexer(行为描述的2 选1MUX)

5-7. Data flow specification of a 2-1 Multiplexer(数据流描述的2 选1MUX)

5-8. Behavioral 4-bit Counter

Description

5-9. 4-bit Full Adder, Using Dataflow Operators 5-10. Behavioral 4-to-1 Multiplexer

Part six

6-1. describe 4-1 MUX with the condition operator

6-2．The logic diagram for a 1-bit full adder is shown in Figure 6-1.Please convert it into a VHDL description

Figure 6-1

7

6-3．Write VHDL code to describe 4-to-1 Multiplexer, Using Logic Equations. 6-4．VHDL code for full-adder using continuous assignment

6-5．VHDL code for a four-bit adder

6-6. Specification of an n-bit adder using arithmetic assignment

6-7. Simple arithmetic logic unit described with the process statement

(用过程语句描述的简单算术逻辑单元)

6-8. Write VHDL code for a D flip-flop.

6-9. Write VHDL code for a D flip-flop with asynchronous reset. 6-10. Write VHDL code for a D flip-flop with synchronous reset. 6-11.

Write VHDL code for A four-bit register with asynchronous clear

6-12. Write VHDL code for an n-bit register with asynchronous clear and enable. 6-13. 6-14. 6-15. 6-16.

Write VHDL code for a three-bit shift register . Correct Wrong code for a three-bit shift register . Write VHDL code for a four-bit counter . Write VHDL code for Flipflop T_FF

6-17 Write VHDL code for Ripple Carry Counter using top-down block design Methodology.

8

Figure 6-2

6-18.Write a Code program for a 4-to-1 multiplexer using the if-else or case 6-19.Write D flip-flop VHDL code with asynchronous reset. 6-20.According to the schematic diagram below, write the program.

Part seven

7-1. Designs a tri-states bidirectional driver(设计一个三态双向驱动器) 7-2.设计一个BCD 码—七段数码管显示译码器

7-3. 分别采用非流水线方式和4 级流水方式实现8位全加器

Part eight

8-1. Designs a 4×4 search table multiplier(设计一个4×4 查找表乘法器)

8-2. Use the limited state machine to design a “101101” the sequence detector(使用有限状态机设计一个“101101”序列检测器 )

Part nine

Read the following program carefully, and draw the entity diagram, and the RTL schematic diagram.

1.entity xiaodou is

port(

din : in STD_LOGIC; clk : in STD_LOGIC; dout : out STD_LOGIC

);

9

end xiaodou;

architecture xiaodou of xiaodou is signal x,y:std_logic; begin process(clk) begin if clk'event and clk='1' then x<=din;

y<=x;

end if;

dout<=x and (not y);

end process;

2.ENTITY reg1 IS PORT ( d : in BIT;

clk : in BIT; q

: out BIT);

END reg1;

ARCHITECTURE reg1 OF reg1 IS SIGNAL a, b : BIT; BEGIN PROCESS (clk) BEGIN

IF clk='1' AND clk’event THEN a <= d; b <= a; q <= b; END IF; END PROCESS;

10

END reg1;

3.LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL; ENTITY TRIS IS

PORT ( CONTROL : IN STD_LOGIC;

INN Q Y

: IN STD_LOGIC; : INOUT STD_LOGIC; : OUT STD_LOGIC );

END TRIS;

ARCHITECTURE ONE OF TRIS IS BEGIN

PROCESS (CONTROL, INN, Q) BEGIN

IF (CONTROL = '0') THEN

Y <= Q; Q <= 'Z';

ELSE

Q <= INN; Y <= 'Z';

END IF;

END PROCESS;

END ONE;

4.ENTITY xiaodou Is

port(

din : in STD_LOGIC; clk : in STD_LOGIC; dout : out STD_LOGIC

11

);

end xiaodou;

architecture xiaodou of xiaodou is signal x,y:std_logic; begin process(clk) begin if clk'event and clk='1' then x<=din;

y<=x;

end if;

dout<=x and (not y);

end process;

5. entity model is

port(clkout : out std_logic); end model;

architecture a_clk of model is signal clk_int : std_logic := 0; begin process begin

wait for 10 ns;

clk_int <= not clk_int; end process; clk_out <= clk_int;

end a_clk;

6. library IEEE;

12

use IEEE.STD_LOGIC_11.all; entity test is

port(

a : in STD_LOGIC; b : in STD_LOGIC; y : out STD_LOGIC

);

end test;

architecture test of test is begin

process(a,b)

variable comb:std_logic_vector(1 downto 0); comb:=a&b; case comb is

when \"00\"=>y<='1'; when \"01\"=>y<='1'; when “10\"=>y<='1'; when “11\"=>y<='0'; when others=>y<='Z';

end case;

end process; end test;

13