DRAM using barrier layer

专利名称：DRAM using barrier layer发明人：Narita, Kaoru, c/o NEC Corporation申请号：EP91109991.9申请日：19910618公开号：EP0462576B1公开日：19941228

摘要：A memory cell comprising a MOSFET formed on a principle surface of asemiconductor substrate and an information storage capacitor having a storageelectrode formed in or on the substrate so as to contact with a drain region of theMOSFET, and a capacitor electrode formed adjacent to the storage electrode with acapacitor insulator film being sandwiched between the storage electrode and thecapacitor electrode. The storage electrode is connected to the drain region of theMOSFET through a thin barrier layer which is formed between the drain region and thestorage electrode region so as to prevent impurities in the storage electrode from beingdiffused into the drain region.

申请人：NEC CORP

地址：JP

国籍：JP

代理机构：Glawe, Delfs, Moll & Partner

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