AT26DF041资料

Features

•Single 3.0V - 3.6V or 2.7V - 3.6V Supply

•Serial Peripheral Interface (SPI) Compatible•33 MHz Max Clock Frequency•Byte Program Operation•

Page Program Operation

–2048 Pages (256 Bytes/Page) Main Memory

–Single Cycle Reprogram Capability (Page Erase and Program)•Supports Optional Page and Block (2 KB or 4 KB) Erase Operations•Continuous Read Capability through Entire Array–Ideal for Code Shadowing Applications

•Hardware Data Protection Feature for the Top KB of Memory•

Low Power Dissipation

–4 mA Active Read Current Typical–2 µA CMOS Standby Current Typical

•5.0V-tolerant Inputs: SI, SCK, CS, and WP Pins•100,000 Program/Erase Cycles Typical•

Data Retention – 20 years

1.Description

The AT26DF041 is a 3.0-volt or 2.7-volt only, serial interface Flash memory ideallysuited for awide variety of program code- and data-storage applications. Its 4,194,304bits of memory are organized as 2048 pages of 256 bytes each. Unlike conventionalFlash memories that are accessed randomly with multiple address lines and a parallelinterface, the DataFlash® uses an SPI serial interface to sequentially access its data.The DataFlash supports SPI mode 0 and mode 3. The simple serial interface facili-tates hardware layout, increases system reliability, minimizes switching noise, andreduces package size and active pin count. The device is optimized for use in manycommercial and industrial applications where high density, low pin count, low voltage,and low power are essential. To allow for simple in-system reprogrammability, theAT26DF041 does not require high input voltages for programming. The device oper-ates from a single power supply, 3.0V to 3.6V or 2.7V to 3.6V, for both the programand read operations. The AT26DF041 is enabled through the chip select pin (CS) andaccessed via a three-wire interface consisting of the Serial Input (SI), Serial Output(SO), and the Serial Clock (SCK).Table 1-1.

Pin Configurations

Pin NameFunctionCSChip Select8-SOIC

8-MLF Top View

SCKSerial ClockCS18VCCCS18VCCSISerial InputSO27NCSO27NCWP36SCKWP36SCKSOSerial OutputGND45SIGND45SIWPHardware Write Protect Pin

4-megabit 3.0-volt Only or 2.7-volt Only Serial Firmware DataFlash®AT26DF041 3495B–DFLSH–8/05元器件交易网www.cecb2b.com

To allow for simple in-system reprogrammability, the AT26DF041 does not require high inputvoltages for programming. The device operates from a single power supply, 3.0V to 3.6V or2.7V to 3.6V, for both the program and read operations. The AT26DF041 is enabled throughthe chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input(SI), Serial Output (SO), and the Serial Clock (SCK).

All program and erase cycles are self-timed, and no separate erase cycle is required whenusing the Page Program with Auto-Erase feature.

2.Block Diagram

WPWPLOGICFLASH MEMORY ARRAYPAGE (256 BYTES)STATUSREGISTERBUFFER (256 BYTES)SCKCSVCCGNDSII/O INTERFACESO3.Memory Array

To provide optimal flexibility, the memory array of the AT26DF041 is divided into three levelsof granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagramillustrates the breakdown of each level and details the number of pages per sector and block.All program operations to the DataFlash occur either on a byte basis or on a page-by-pagebasis; however, the optional erase operations can be performed at the block or page level.

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4.Memory Architecture Diagram

Block Erase Detail

Block Address

4KB Internal2KBSectorBlock Erase

Block Address

RangeBlock Erase

(20hCommand)

Architecture(50hCommand)

Range7FFFFh – 7F000h4KBSector 5

2KB7FFFFh – 7F800h2KB7F7FFh – 7F000h7EFFFh – 7E000h4KB2KB7EFFFh – 7E800h2KB7E7FFh – 7E000h7DFFFh – 7D000h

4KB

2KB7DFFFh – 7D800h2KB

7D7FFh – 7D000h

..Sector 4

.

(62KB)

...

71FFFh – 71000h4KB2KB71FFFh – 71800h2KB717FFh – 71000h70FFFh – 70000h4KB2KB70FFFh – 70800h2KB707FFh – 70000h6FFFFh – 6F000h4KB2KB6FFFFh – 6F800h2KB6F7FFh – 6F000h6EFFFh – 6E000h

4KB

2KB6EFFFh – 6E800h2KB

6E7FFh – 6E000h

...

Sector 3

(KB)

...

61FFFh – 61000h4KB2KB61FFFh – 61800h2KB617FFh – 61000h60FFFh – 60000h4KB2KB60FFFh – 60800h2KB607FFh – 60000h5FFFFh – 5F000h4KB2KB5FFFFh – 5F800h2KB5F7FFh – 5F000h5EFFFh – 5E000h

4KB

2KB5EFFFh – 5E800h2KB

5E7FFh – 5E000h

...

Sector 2

(128KB)

...

41FFFh – 41000h4KB2KB41FFFh – 41800h2KB417FFh – 41000h40FFFh – 40000h4KB2KB40FFFh – 40800h2KB407FFh – 40000h3FFFFh – 3F000h4KB2KB3FFFFh – 3F800h2KB3F7FFh – 3F000h3EFFFh – 3E000h

4KB

2KB3EFFFh – 3E800h2KB

3E7FFh – 3E000h

...

Sector 1

(128KB)

...

21FFFh – 21000h4KB2KB21FFFh – 21800h2KB217FFh – 21000h20FFFh – 20000h4KB2KB20FFFh – 20800h2KB207FFh – 20000h1FFFFh – 1F000h4KB2KB1FFFFh – 1F800h2KB1F7FFh – 1F000h1EFFFh – 1E000h

4KB

2KB1EFFFh – 1E800h2KB

1E7FFh – 1E000h

...

Sector 0

(128KB)

...

01FFFh – 01000h4KB2KB01FFFh – 01800h2KB017FFh – 01000h00FFFh – 00000h

4KB

2KB00FFFh – 00800h2KB

007FFh – 00000h

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AT26DF041

Page Erase Detail

4KB 2KB256 ByteBlock Erase

Block Erase

Page Erase

Page Address

(20hCommand)

(50hCommand)

(81hCommand)

Range256 Bytes7FFFFh – 7FF00h256 Bytes7FEFFh – 7FE00h256 Bytes7FDFFh – 7FD00h2KB

256 Bytes7FCFFh – 7FC00h256 Bytes7FBFFh – 7FB00h256 Bytes7FAFFh – 7FA00h256 Bytes7F9FFh – 7F900h4KB

256 Bytes7F8FFh – 7F800h256 Bytes7F7FFh – 7F700h256 Bytes7F6FFh – 7F600h256 Bytes7F5FFh – 7F500h2KB

256 Bytes7F4FFh – 7F400h256 Bytes7F3FFh – 7F300h256 Bytes7F2FFh – 7F200h256 Bytes7F1FFh – 7F100h256 Bytes

7F0FFh – 7F000h

.........

256 Bytes00FFFh – 00F00h256 Bytes00EFFh – 00E00h256 Bytes00DFFh – 00D00h2KB

256 Bytes00CFFh – 00C00h256 Bytes00BFFh – 00B00h256 Bytes00AFFh – 00A00h256 Bytes009FFh – 00900h4KB

256 Bytes008FFh – 00800h256 Bytes007FFh – 00700h256 Bytes006FFh – 00600h256 Bytes005FFh – 00500h2KB

256 Bytes004FFh – 00400h256 Bytes003FFh – 00300h256 Bytes002FFh – 00200h256 Bytes001FFh – 00100h256 Bytes000FFh – 00000h

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5.Device Operation

The device operation is controlled by instructions from a host processor. The list of instructionsand their associated opcodes are contained in Tables 1 through 3. A valid instruction startswith the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer ormain memory address location. While the CS pin is low, toggling the SCK pin controls theloading of the opcode and the desired buffer or main memory address location through the SI(serial input) pin. All instructions, addresses and data are transferred with the most significantbit (MSB) first.

Main memory addressing is referenced using the terminology A23-A0.

5.1Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from eitherone of the two data buffers.

5.1.1

Continuous Array Read

The Continuous Array Read command can be used to sequentially read a continuous streamof data from the device by simply providing a clock signal once the initial starting address hasbeen specified. The device incorporates an internal address counter that automatically incre-ments on every clock cycle.

Two opcodes, 0BH and 03H, can be used for the Continuous Array Read command. The useof each opcode depends on the maximum SCK frequency that will be used to read data fromthe device. The 0BH opcode can be used at any SCK frequency up to the maximum specifiedby fCAR1. The 03H opcode can be used for lower frequency read operations up to the maxi-mum specified by fCAR2.

To perform a Continuous Array Read, the CS pin must first be asserted and the appropriateopcode must be clocked in. After the opcode has been clocked in, three address bytes (24 bitsrepresenting A23-A0) must be clocked in to specify the starting address location of the firstbyte to read within the memory array. Since the upper address limit of the device is 07FFFFh,the first five address bits (A23-A19) will be ignored. If the 0BH opcode is used, one don't carebyte must also be clocked in after the three address bytes.

After the three address bytes (and the one don't care byte if using opcode 0BH) have beenclocked in, additional pulses on the SCK pin will result in serial data being output on the SO(serial output) pin. The data is always output with the most-significant bit (MSB) of a byte first.When the last bit of the memory array has been read, the device will continue reading back atthe beginning of the array (000000h). No delays will be incurred when wrapping around fromthe end of the array to the beginning of the array.

Deasserting the CS pin (a low-to-high transition) will terminate the read operation and put theSO pin into a high-impedance state. The Continuous Array Read command bypasses bothdata buffers and leaves the contents of the buffers unchanged.

5.1.2

Status Register Read

The status register can be used to determine the device’s Ready/Busy status or the devicedensity. To read the status register, an opcode of 05H must be loaded into the device. Afterthe last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB(bit 7), will be shifted out on the SO pin during the next eight clock cycles. After bit 0 of the sta-tus register has been shifted out, the sequence will repeat itself (as long as CS remains low4

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AT26DF041

and SCK is being toggled) starting again with bit 7. The data in the status register is constantlyupdated, so each repeating sequence will output new data.Table 5-1.

Bit 7X

Status Register Format

Bit 6X

Bit 50

Bit 41

Bit 31

Bit 21

Bit 1X

Bit 0RDY/BUSYReady/Busy status is indicated using bit 0 of the status register. If bit 0 is a 0, then the deviceis not busy and is ready to accept the next command. If bit 0 is a 1, then the device is in a busystate. The user can continuously poll bit 0 of the status register by stopping SCK at a low levelonce bit 0 has been output. The status of bit 0 will continue to be output on the SO pin, andonce the device is no longer busy, the state of SO will change from 1 to 0. There are five oper-ations which can cause the device to be in a busy state: Page Erase, Block Erase, ByteProgram, Page Program, and Page Program with Auto-Erase.

The device density is indicated using bits 5, 4, 3 and 2 of the status register. For theAT26DF041, the four bits are 0, 1, 1 and 1. The decimal value of these four binary bits doesnot equate to the device density; the four bits represent a combinational code relating to differ-ing densities of Serial DataFlash devices, allowing a total of 16 different densityconfigurations.

Bits 7, 6, and 1 of the status register will contain undefined data.

5.2

5.2.1

Program and Erase Commands

Byte Program

The Byte Program command can be used to program a single byte of data into a previouslyerased memory location. An erased memory location is one that has all eight bits set to thelogical “1” state (a byte value of FFH).

The perform a Byte Program operation, an opcode of 02H must be clocked into the device fol-lowed by the 24-bit address sequence denoting which byte location to program. Since theupper address limit of the device is 07FFFFh, address bits A23-A19 are ignored. After alladdress bits have been shifted in, the device will take the one byte of data from the SI pin andstore it in the internal buffer. If more than one byte of data is clocked in, then only the last byteof data sent will be stored in the buffer.

When the CS pin is deasserted (low-to-high transition), the device will take the one byte storedin the internal buffer and program it into the main memory array at the location specified byA18-A0. The programming of the byte is internally self-timed and should take place in a max-imum time of tBP. During this time, the status register will indicate that the device is busy.

5.2.2Page Program

An entire previously erased page in the main memory can be programmed by using the PageProgram command. Data is first shifted into the internal buffer and then programmed into thespecified page in main memory. To start the operation, an opcode of 11H must be clocked intothe device followed by the 24-bit address sequence. Address bits A23-A19 are ignored sincethe upper address limit of the device is 07FFFFh. After all address bits have been shifted in,the device will take data from the SI pin and store it in the buffer starting at the first byte loca-tion specified by A7-A0. If the end of the buffer is reached, the device will wrap around backto the beginning of the buffer. When there is a low-to-high transition on the CS pin, the devicewill program the data stored in the buffer into the specified page in the main memory. It is nec-5

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essary that the page in the main memory has been previously erased. The programming ofthe page is internally self-timed and should take place in a maximum time of tP. During thistime, the status register will indicate that the device is busy.

Successive page programming operations without doing a page erase are not recommended.In other words, changing bytes within a page from a “1” to a “0” during multiple page program-ming operations without erasing that page is not recommended.

5.2.3

Page Program with Auto-Erase

This operation functions similarly to the Page Program command except that the device willautomatically erase the addressed page in the main memory before it programs the page,thereby eliminating the need to pre-erase the page or a block of memory. To initiate the oper-ation, the 8-bit opcode of 82H must be clocked into the device followed by the 24-bit addresssequence (A23-A0). Since the upper address limit of the device is 07FFFFh, the five mostsignificant bits (A23-A19) are ignored. After all address bits are shifted in, the device will takedata from the SI pin and store it in the internal buffer. If the end of the buffer is reached, thedevice will wrap around back to the beginning of the buffer. When there is a low-to-high transi-tion on the CS pin, the part will first erase the selected page in main memory to all 1s and thenprogram the data stored in the buffer into the specified page in the main memory. Both theerase and the programming of the page are internally self-timed and should take place in amaximum of time tEP. During this time, the status register will indicate that the part is busy.

Because of the single page erase granularity, care must be taken to preserve data integritywithin the memory array when using the Page Program with Auto-Erase command. If multiplepages of data within a sector are modified in a random fashion numerous times while certainpages within the same sector are never modified or modified infrequently, then the systemmust ensure that each page within the sector is updated/rewritten, or “refreshed”, at least oncewithin every 10,000 cumulative page erase operations to that sector. For example, if the firstsix pages of a sector are used to store static data and the remaining pages are used to storechanging data, then the first six pages of the sector must be “refreshed” within 10,000 cumula-tive page erase operations to that sector. The pages used to store the changing data do notneed to be “refreshed” provided that the pages are updated sequentially or in such a fashionthat guarantees that each page is rewritten on a fairly even basis.

5.2.4

Page Erase

The optional Page Erase command can be used to individually erase any page in the mainmemory array allowing the Page Program or Byte Program commands to be utilized at a latertime. To perform a Page Erase, an opcode of 81H must be loaded into the device followed bythe 24-bit address sequence. Address bits A23 - A19 are ignored since the upper address limitof the device is 07FFFFh. In addition, address bits A7-A0 are ignored since a full page ofdata is being erased. When a low-to-high transition occurs on the CS pin, the part will erasethe selected page to 1s. The erase operation is internally self-timed and should take place in amaximum time of tPE. During this time, the status register will indicate that the part is busy.Because of the single page erase granularity, care must be taken to preserve data integritywithin the memory array when using the Page Erase command. If multiple pages of datawithin a sector are modified in a random fashion numerous times while certain pages withinthe same sector are never modified or modified infrequently, then the system must ensure thateach page within the sector is updated/rewritten, or “refreshed”, at least once within every10,000 cumulative page erase operations to that sector. For example, if the first six pages of asector are used to store static data and the remaining pages are used to store changing data,

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then the first six pages of the sector must be “refreshed” within 10,000 cumulative page eraseoperations to that sector. The pages used to store the changing data do not need to be“refreshed” provided that the pages are updated sequentially or in such a fashion that guaran-tees that each page is rewritten on a fairly even basis.

5.2.5

Block Erase (2 Kbytes)

A block of 2Kbytes (eight pages) can be erased at one time allowing the Page Program orByte Program commands to be utilized to reduce programming times when writing largeamounts of data to the device. To perform a 2KB Block Erase, an opcode of 50H must beloaded into the device, followed by the 24-bit address sequence. As stated previously,address bits A23-A19 are ignored. In addition, address bits A10-A0 are ignored since a fullblock of eight pages is being erased, but any address within the block can be used. When alow-to-high transition occurs on the CS pin, the part will erase the selected block of eightpages to 1s. The erase operation is internally self-timed and should take place in a maximumtime of tBE1. During this time, the status register will indicate that the part is busy.Block Erase (4 Kbytes)

A block of 4 Kbytes (16 pages) can be erased at one time allowing the Page Program or ByteProgram commands to be utilized to reduce programming times when writing large amounts ofdata to the device. To perform a 4KB Block Erase, an opcode of 20H must be clocked into thedevice followed by the 24 bit address sequence (A23-A0), of which address bits A23-A19are ignored since the upper address limit of the device is 07FFFFh. In addition, address bitsA11-A0 are ignored since a full block of 16 pages is being erased; however, any addresswithin the block can be used to specify which block to erase. When the CS pin is deasserted,the device will erase the selected block of 16 pages to logical 1s. The erase operation is inter-nally self-timed and should take place in a maximum of time of tBE2. During this time, the statusregister will indicate that the device is busy.

5.2.6

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6.Manufacturer and Device ID Read

This instruction allows the user to read the Manufacturer ID, Device ID, and Extended Device Information. A 1-byte opcode,9FH, must be clocked into the device while the CS pin is low. After the opcode is clocked in, the Manufacturer ID, 2 bytes ofDevice ID and Extended Device Information will be clocked out on the SO pin. The fourth byte of the sequence output is theExtended Device Information String Length byte. This byte is used to signify how many bytes of Extended Device Informa-tion will be output. Reading the Extended Device Information String Length (byte 4) and any subsequent information isoptional.

6.1

6.1.1

Hex Value

1FH

Manufacturer and Device ID Information

Byte 1 – Manufacturer ID

JEDEC Assigned Code

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

1

Bit 3

1

Bit 2

1

Bit 1

1

Bit 0

1

Manufacturer ID1FH = Atmel

6.1.2

Hex Value

44H

Byte 2 – Device ID (Part 1)

Family CodeBit 7

0

Density Code

Bit 4

0

Bit 6

1

Bit 5

0

Bit 3

0

Bit 2

1

Bit 1

0

Bit 0

0

Family CodeDensity Code

010 = AT26xxx Series00100 = 4-Mbit

6.1.3

Hex Value

00H

Byte 3 – Device ID (Part 2)

MLC CodeBit 7

0

Product Version Code

Bit 5

0

Bit 6

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

MLC CodeProduct Version

000 = 1-bit/cell Technology00000 = Initial version

6.1.4

Hex Value

00H

Byte 4 – Extended Device Information String Length

Byte Count

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

Byte Count00H = 0 Bytes of Information

CSSI9FHOpcodeSO1FHManufacturer IDByte n44HDevice IDByte 100HDevice IDByte 200HExtendedDevice InformationString LengthDataExtendedDevice InformationByte xDataExtendedDevice InformationByte x + 1Each transition represents8 bits and 8 clock cyclesNote:

This information would only be output if the Extended Device Information String Length value was somethingother than 00H.Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be comprised of any number of bytes. Some manufacturers may have Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte.

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7.Pin Descriptions

7.1

Serial Input (SI)

The SI pin is an input-only pin and is used to shift data into the device. The SI pin is used for alldata input including opcodes and address sequences.

7.2Serial Output (SO)

The SO pin is an output-only pin and is used to shift data out from the device.

7.3Serial Clock (SCK)

The SCK pin is an input-only pin and is used to control the flow of data to and from theDataFlash. Data is always clocked into the device on the rising edge of SCK and clocked outof the device on the falling edge of SCK.

7.4Chip Select (CS)

The DataFlash is selected when the CS pin is low. When the device is not selected, data willnot be accepted on the SI pin, and the SO pin will remain in a high-impedance state. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition onthe CS pin is required to end an operation.7.5Write Protect (WP)

If the WP pin is held low, the top 256 pages (K-bytes of address locations 07FFFFh to070000h) of the main memory cannot be reprogrammed. The only way to reprogram the top256 pages is to first drive the protect pin high and then use the program commands previouslymentioned. If this pin and feature are not utilized it is recommended that the WP pin be drivenhigh externally.

8.Power-on/Reset State

When power is first applied to the device, or when recovering from a reset condition, thedevice will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, anda high-to-low transition on the CS pin will be required to start a valid instruction. The SPI modewill be automatically selected on every falling edge of CS by samplingthe inactive clock state.After power is applied and VCC is at the minimum datasheet value, the system should wait 20ms before an operational mode is started.

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Table 8-1.

Command

Read Commands

Opcode

0BH03H05H9FH

0000 10110000 00110000 01011001 1111

AddressBytes

3300

Dummy Bytes

1000

Data Bytes 1+1+1+ 1+

Continuous Array Read

Continuous Array Read (Low Frequency)Status Register Read

Manufacturer and Device ID Read

Table 8-2.

CommandPage Erase

Erase and Program Commands

Opcode81H50H20H02H11H82H

1000 00010101 00000010 00000000 00100001 00011000 0010

AddressBytes

333333

DummyBytes

000000

DataBytes0001256256

Block Erase (2KB)Block Erase (4KB)Byte ProgramPage Program

Page Program with Auto-EraseNotes:

1.Address bits A23-A19 are don’t care bits because the upper address limit of the device is 07FFFFh.

Address bits A7-A0 are don’t care for the Page Erase Command.

Address bits A10-A0 are don’t care for the 2 KB Block Erase Command.Address bits A11-A0 are don’t care for the 4 KB Block Erase Command.

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9.Electrical Specifications

Table 9-1.

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Temperature under Bias................................-55°C to +125°CStorage Temperature.....................................-65°C to +150°CAll Input Voltages(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25VAll Output Voltages

with Respect to Ground.............................-0.6V to VCC + 0.6V

Table 9-2.DC and AC Operating Range

AT26DF041

Ind.

-40°C to 85°C2.7V to 3.6V

Operating Temperature (Case)VCC Power Supply(1)Note:

1.After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an opera-tional mode is started.

Table 9-3.

SymbolISB

DC Characteristics

ParameterStandby Current

Condition

CS, WP = VCC, all inputs at CMOS levels

f = 33 MHz; IOUT = 0 mA; VCC = 3.6V

f = 20 MHz; IOUT = 0 mA; VCC = 3.6VVCC = 3.6VVIN = CMOS levelsVI/O = CMOS levels

Min

Typ28415

Max10151035110.6

2.0

IOL = 1.6 mA; VCC = 2.7VIOH = -100 µA

VCC - 0.2V

0.4

UnitsµAmAmAmAµAµAVVVV

ICC1

Active Current, Read Operation

Active Current,

Program/Erase OperationInput Load CurrentOutput Leakage CurrentInput Low VoltageInput High VoltageOutput Low VoltageOutput High Voltage

ICC2ILIILOVILVIHVOLVOH

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Table 9-4.AC Characteristics

AT26DF041

2.7V Vcc

3.0V VccMin

Max333320

13131002020330

12151230581012

10111230581012

UnitsMHzMHzMHznsnsnsnsnsnsnsnsnsnsmsµsmsmsmsms

SymbolfSCKfCAR1fCAR2tWHtWLtCStCSStCSHtSUtHtHOtDIStVtEPtBPtPtPEtBE1tBE2

ParameterSCK Frequency

SCK Frequency for Continuous Array Read

SCK Frequency for Continuous Array Read (Low Frequency)SCK High TimeSCK Low TimeMinimum CS High TimeCS Setup TimeCS Hold TimeData In Setup TimeData In Hold TimeOutput Hold TimeOutput Disable TimeOutput Valid

Page Erase and Programming TimeByte Program TimePage Programming TimePage Erase TimeBlock Erase (2KB) TimeBlock Erase (4KB) Time

MinMax252520

18181002020550

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10.Input Test Waveforms and Measurement Levels

ACDRIVINGLEVELS2.4V2.00.8ACMEASUREMENTLEVEL0.45VtR, tF < 3 ns (10% to 90%)

11.Output Test Load

DEVICEUNDERTEST30 pF12.AC Waveforms

Two different timing diagrams are shown below. Waveform 1 shows timing that is compatiblewith SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3. The setupand hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.Figure 12-1.Waveform 1 – SPI Mode 0

tCSCStCSSSCKtVSOHIGH IMPEDANCEtSUSIVALID INtHtHOVALID OUTtDISHIGH IMPEDANCEtWHtWLtCSHFigure 12-2.Waveform 2 – SPI Mode 3

tCSCStCSSSCKtVSOHIGH ZtSUSIVALID INtHOVALID OUTtHtDISHIGH IMPEDANCEtWLtWHtCSH13

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Figure 12-3.Command Sequence for Read/Write Operations (except Status Register Read)

SICMD8 bits8 bits8 bitsADDRESS BYTESMSBX X X XX X X XX X X XX X X XX X X XX X X XLSBA23-A16A15-A8A7-A013.Write Operations

The following waveforms illustrate the various write sequences available.

Figure 13-1.Byte Program

· Starts self-timed program operationCSSICMDA23-A16A15-A8A7-A0nFigure 13-2.Page Program

· Completes writing into selected buffer· Starts self-timed erase/program operationCSSICMDA23-A16A15-A8A7-A0nn+1Last ByteEach transition represents8 bits and 8 clock cyclesn = 1st byte readn+1 = 2nd byte read14.Read Operations

The following waveform illustrates the read sequence available.

Figure 14-1.Continuous Array Read

Don't Care byte not needed for Low Frequency read (03H opcode)CSSISOEach transition represents8 bits and 8 clock cyclesCMDA23-A16A15-A8A7-A0Xnn+1n = 1st byte readn+1 = 2nd byte read14

AT26DF041

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AT26DF041

15.Detailed Bit-level Read Timing – SPI Mode 0

15.1

Continuous Array Read (Opcode 0BH)

CSSCK12383940414243tSUSI00XXXtVLSBMSBSOHIGH-IMPEDANCEDATA OUTD7D6D5D2D1D0D7D6D5BIT 0BIT 7OFOFBYTE nBYTE n+115.2Continuous Array Read (Low Frequency: Opcode 03H)

CSSCK12303132333435tSUSI00XXXtVTA OUTLSBMSBSOHIGH-IMPEDANCEDAD7D6D5D2D1D0D7D6D5BIT 0BIT 7OFOFBYTE nBYTE n+115.3Status Register Read (Opcode: 05H)

CSSCK12345671011121617tSUCOMMAND OPCODESI00000101tVSTATUS REGISTER OUTPUTSOHIGH-IMPEDANCED7D6D5D4D1D0D7MSBLSBMSB3495B–DFLSH–8/05

15

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16.Detailed Bit-level Read Timing – SPI Mode 3

16.1

Continuous Array Read (Opcode 0BH)

CSSCKtSUSI12394041424300XXXtVSOHIGH-IMPEDANCEDATA OUTD7D6D5D2D1LSBD0MSBD7D6D5BIT 0OFBYTE nBIT 7OFBYTE n+116.2Continuous Array Read (Low Frequency: Opcode 03H)

CSSCKtSUSI12313233343500XXXtVSOHIGH-IMPEDANCEDATA OUTD7D6D5D2D1LSBD0MSBD7D6D5BIT 0OFBYTE nBIT 7OFBYTE n+116.3Status Register Read (Opcode: 05H)

CSSCKtSUSI123456710111217COMMAND OPCODE00000101tVSOHIGH-IMPEDANCED7MSBSTATUS REGISTER OUTPUTD6D5D4D0LSBD7MSBD616

AT26DF041

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AT26DF041

17.Ordering Information

17.1

Green Packages (Pb/Halide-free/RoHS Compliant)

ICC (mA)Active15

Standby0.01

Ordering CodeAT26DF041-MUAT26DF041-SU

Package8M1-A8S2

Operation RangeIndustrial(-40°C to 85°C)

fSCK (MHz)33

Package Type

8M1-A8S2

8-contact, 5mm x 6mm Very Thin Micro Lead-Frame Package (MLF)8-lead, 0.209\" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

17

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18.Packaging Information

18.1

8M1-A – MLF

DD10Pin 1 IDEE1SIDE VIEWTOP VIEWA2A3A1 A0.08CD2COMMON DIMENSIONS(Unit of Measure = mm)SYMBOLMINNOMMAXNOTEePin #1 Notch(0.20 R) A A1 E2– 0.85 1.00 – – 0.05 0.35 3.20 3.80 0.50 0.65 TYP0.20 TYP0.40 6.00 TYP5.75 TYP3.40 5.00 TYP4.75 TYP4.00 1.270.60 1.30 REF0.7512o4.203.600.48 A2 A3 b b D LK D1 D2 E E1 E2 e L 0 BOTTOM VIEW K 12/6/04TITLE 2325 Orchard Parkway8M1-A, 8-lead, 6 x 5 x 1.00 mm Body, Very Thin Dual Flat Package San Jose, CA 95131No Lead (MLF)DRAWING NO.8M1-AREV. AR18

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AT26DF041

18.2

8S2 – EIAJ SOIC

C1EE1NL∅Top ViewEnd VieweASYMBOLbCOMMON DIMENSIONS(Unit of Measure = mm)MINNOMMAXNOTEA1A 1.70 2.16 A1 0.05 b 0.35 0.25 0.48 5C 0.15 0.35 5DD 5.13 5.35 E1 5.18 5.40 2, 3E 7.70 8.26 L 0.51 0.85 ∅ Side View 0° 8° 4e 1.27 BSC Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs are not included. 3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.10/7/032325 Orchard ParkwaySan Jose, CA 95131TITLE8S2, 8-lead, 0.209\" Body, Plastic Small Outline Package (EIAJ)DRAWING NO.R8S2REV. C19

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